Dell USA L.p.

Dell Corporate Services Corporation

Other

Michael D Durkin

Orin Michael Ozias

Pearce R Jones

Charles P Zeller

John P Busch

Thomas J Kocis

Mark B Penniman

Thomas H Holman, Jr

Dan E Swindler

Thomas Shu

Greg N Stewart

Terry J Parks

David R Lunsford

Derek Westmoreland

A docking station structure is used to operatively connect a notebook computer to desktop computer peripheral devices. The docking station has an internal receiving chamber into which the portable computer may be manually inserted, an electrical connector positioned within the receiving chamber, a travel plate movably carried within the receiving chamber, a motorized drive system operative to drive the travel plate toward and away from the electrical connector, and a latch structure carried by the travel plate for movement therewith. With the travel plate in a wait position thereof, the portable computer is rearwardly inserted into the receiving chamber. In response to such insertion, the latch structure automatically locks the computer to the travel plate, and the drive system rearwardly moves the travel plate to mate the electrical connector with a corresponding connector on the computer, thereby operatively linking the computer to the peripheral devices. To remove the computer, the drive system is operated to forwardly move the drive plate and the computer to an ejection position in which the computer and docking station electrical connector structures are disconnected from one another, and the computer is unlocked from the travel plate. Upon insertion of the computer into the docking station opposite side portions of the computer are slidingly received in docking station track indentations operative to maintain the computer in a precisely aligned relationship with the docking station electrical connector during driven movement of the computer.

Motorized portable computer/expansion chassis docking system

A digital computer system includes a central processor unit (CPU) and an optional co-processor unit, both connected to a local bus. The co-processor unit, when installed, fits into a socket having pins, the pins being connected to communicate with the CPU through the local bus. A presence-detect circuit is connected to the local bus and receives a signal indicating the presence of the co-processor unit in the socket. Logic circuitry receives the output signal from the presence-detect circuit and provides a READY-- signal in either the presence or absence of the co-processor unit.

Circuit for detection of co-processor unit presence and for correction

A digital computer system includes an interface for routing data which permits the transfer of data between mismatched devices. The computer system comprises a processor, memory and an interconnecting data bus, all configured to handle data units of a first data width. Also connected to the data bus is at least one I/O device configured to handle data units of a second data width. By adjusting the width of the data being transferred to match the width of the receiving device or bus, data may be transferred between devices of differing width. To adjust the width, control means are provided which modify the route along which data bytes are transferred based upon the width of the transferring and receiving devices and the direction of transfer are provided.

Configurable interface for routing data between mismatched devices

A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter. The requesting master device is transferred into the address master state while the selected master device is still in the data master state, thus performing a pipelining operation.

Multi-master bus arbitration system in which the address and data lines

A memory circuit for use in a data processing system is accessed by address signals and includes interconnection circuitry for at least one memory module. The memory circuit further includes an address buffer for transmitting the address signals to the interconnection circuits if and only if the at least one memory module is present. A line interconnects the output enable pin of an address buffer to a grounded PRESENT (PRES) pin on a (single in-line memory module (SIMM) when it is installed in a socket. The line to the address buffer enable pin includes a pull-up resistor portion so that the address buffer is disabled unless a SIMM is connected to the socket.

Memory system and associated method for disabling address buffers

A digital computer system has internal and external devices, with the external devices connected to an associated bus. The digital computer system has a clock frequency which is different from that of the associated bus. Memory addresses from the central processor are decoded and for external devices, a frequency adjusting circuit divides the output from a clock oscillator to provide a system clock that is approximately the same frequency as that of the associated bus.

System for adapting its clock frequency to that of an associated bus

A digital computer system has a central processor unit (CPU). A computer program, entered into the digital computer system for execution thereof, has a program code word embedded at an arbitrary location therein. An addressable programmable array of logic (PAL) is operatively connected to the CPU for receiving a READ signal originated by the CPU at the address of the PAL, the being programmed to output a portion of a preset array code word in a response to the READ signal, and to output the remainder of the array code word in segments in response to subsequent READ signals at the same address. A data bus, connected to receive and transmit the portion and remainders of the array code word to the CPU for comparison with the program code word. The program code word and the array code word are compared and, if identical permit use of the program and do not permit use when the program code word and the array code word are not identical.

Digital computer code word identification system

An electronic digital computer has a warning facility for indicating activity and operation, or lack of same, of the central processor in the system. It is done by providing a signal indicative of continuing operation of the central processor to activate an indicator circuit. The indicated circuit utilizes an RC circuit for maintaining a high level through a high comparator when the processor is operational. When the central processor becomes non-operational, the capacitor discharges to a point where a low comparator responds, causing the capacitor to begin charging to its high value. The associated circuits, using this feature, maintain an LED in the active stage until such time as there is no signal indicating continuing operation of the central processor, at which time the LED begins an approximate 50% duty cycle resulting in a blinking indicator.

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Austin, TX, United States of America

Michael D Durkin