Sun Microsystems, Inc.

Oracle International Corporation

Michael D Derbish

Gavin G Gibson

John D Acton

Hugh M Humphreys

Steven E Schelong

William B DeRolf

Steven P Kent

Jack M Hardy, Jr

Ricardo Yong

Simon Yiu Hoi Poon

Cornelia Luise Edeltraut Koch-Stoschek

Cheng Yang

Xianda Ma

Rambabu Lolabattu

Mark Farabaugh

Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a 'black box' regarding FPGA I/O during the occurrence of the catastrophic events within the system.

System and method for filtering field programmable gate array input/output

A method for battery condition testing. In one embodiment, the method is comprised of interrupting AC power service to a data storage system. The interruption causes an exhaustible power source to provide operating power to the data storage system. The exhaustible power source is coupled to said data storage system. The exhaustible power source is adapted to provide operating power to the data storage system when the AC power service to the data storage system is interrupted. The method is further comprised of discharging the exhaustible power source by operating the data storage system with the exhaustible power source for a specified period of time less than full discharge but sufficient to fully flush the cache. The exhaustible power source passes the condition testing provided the exhaustible power source provides operating power to the data storage system for the specified period of time. The method is further comprised of recharging the exhaustible power source subsequent to the exhaustible power source passing the condition testing.

Method for monitoring the condition of a battery in a high temperature high current environment

A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.

Data processing system including a shared memory resource circuit

A data processing system includes a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node. In one construction, this processing node has a processor, a printed circuit board, a memory partitioned into first and second sections and a local bus connecting the processor, a block sharable memory section of the memory, and the printed circuit board. The local bus is used for transferring data in parallel from the processor to a directly sharable memory section of the memory on the printed circuit board and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sensed data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial data bus to the next successive processing node, a receiver for receiving serialized data from next preceding processing node, and a deserializer for deserializing the received serialized data into parallel data.

Computing system having multiple nodes coupled in series in a closed loop

Multiprocessor distributed memory system and board and methods therefor

Growing community of inventors

Coral Springs, FL, United States of America

Michael D Derbish