Intersil Americas Inc.

Harris Corporation

Intersil Corporation

Other

Michael D Church

Alexander Kalnitsky

John T Gasner

Chris A McCarty

Paul E Bakeman, Jr

Hosam Haggag

Edgardo A Laber

Akira Ito

David A Decrosta

Sameer D Parab

Robert Lomenick

Dev Alok Girdhar

Yun Yue

Kantilal Bacrania

Lawrence Pearce

Stephen Joseph Gaul

Prabhjot Singh

Choong-Sun Rhee

Anthony L Rivoli

George V Rouse

George S Bajor

John W Butler

Donald Frank Hemmenway

Jose Avelino Delgado

Jeffrey Michael Johnston

Brent Raymond Doyle

Glenn Alan DeJong

Thomas Andrew Jochum

Robert T Fuller

Gregory J Fisher

James Edwin Vinson

Glenn A Dejong

Robert Lomenic

Dave Kutchmarick

Jeffrey M Johnston

Michael Ray Jayne

Stephen Jospeh Gaul

Paul E Bakeman

Robert L Lomenick

Paul E Bakeman Jr

An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.

Method of forming an insulator layer in a semiconductor structure and structures resulting therefrom

A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Active area bonding compatible high current structures

A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.

Ballasted polycrystalline fuse

An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Method of manufacturing junction barrier schottky diode with dual silicides

A method and structure for a semiconductor device which provides for an etch of a metal layer such as an interconnect layer which does not affect a thinner layer such as a thin film resistor (TFR) layer, such as a circuit resistor. In one embodiment, a TFR resistor layer is protected by a patterned protective layer during an etch of the metal layer, and provides an underlayer for the metal layer. In another embodiment, the TFR layer is formed after providing the patterned metal layer. The metal layer can provide, for example, end caps for the circuit resistor.

Thin film resistor

A junction barrier Schottky diode has N-type well having a surface and first peak impurity concentration; P-type anode region in surface of the well having second peak impurity concentration; N-type cathode contact region in surface of the well and laterally spaced from a first wall of the anode region having third peak impurity concentration; and first N-type region in surface of the well and laterally spaced from second wall of the anode region having fourth impurity concentration. Center of the spaced region between the first N-type region and the second wall of the anode region has fifth peak impurity concentration. Ohmic contact is made to the anode region and cathode contact region. Schottky contact is made to the first N-type region. First and fifth peak impurity concentrations are less than the fourth peak impurity concentration. The fourth peak impurity concentration is less than the second and third peak impurity concentrations.

Junction barrier Schottky diode

A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Flash memory array of floating gate-based non-volatile memory cells

A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

Memory array of floating gate-based non-volatile memory cells

A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide

A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

A 'tabbed' MOS device provides radiation hardness while supporting reduced gate width requirements. The 'tabbed' MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the &#x201c;tabbed&#x201d; MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Method for fabricating a radiation hardened device

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Sebastian, FL, United States of America

Michael D Church