Dell Products Inc.

Other

Michael D Christensen

Yuwei Cai

Mukund Purshottam Khatri

Wei G Liu

An information handling system collects system configuration information during a boot process, and builds a bifurcation table for root ports of the information handling system. The system also initiates a bifurcation of the root ports in parallel to loading an operating system of the data processing unit, and disables one of the root ports that is associated with the data processing unit. In response to determining that the operating system of the data processing unit has finished loading, the system enables the root port associated with the data processing unit. The bifurcation of the root port associated with the data processing unit is performed later when a peripheral component interconnect-express endpoint associated with the data processing unit is ready.

Boot time reduction for an information handling system with a data processing unit

An information handling system includes a memory, and a basic input/output system (BIOS). The BIOS receives a request to map multiple processor cores to multiple integrated memory controllers of a multiple core processor. In response to the reception of the request, the BIOS calculates a different latency for each of the processor cores. Based on the calculated different latency for each of the processor cores, the BIOS assigns mapping priority levels to the processor cores of the multiple core processor. Based on the mapping priority levels, the BIOS maps each of the processor cores to an associated one of the integrated memory controllers. The BIOS stores the map of the processor cores in the memory.

Core mapping based on latency in a multiple core processor

An information handling system includes a model-specific register and a basic input/output system (BIOS). The BIOS receives a selection of a number of processor cores to have enabled in a multiple core processor. In response to the reception of the selection of the number of processor cores to have enabled, the BIOS calculates a different latency for each of a plurality of processor cores in the multiple core processor. Based on the calculated different latency for each of the processor cores, the BIOS determines a first subset of the processor cores to enable and a second subset of the processor cores to disable. The BIOS sets bits in the model-specific register to indicate that the first subset of the processor cores is enabled and the second subset of the processor cores is disabled.

Disabling processor cores for best latency in a multiple core processor

A system and method for tracking bootable devices are disclosed which provide significant advantages over current computer system device management techniques. A system incorporating teachings of the present disclosure may include one or more installed bootable devices and a computer readable medium storing identification data for each of the installed bootable devices. The identification data may include host bridge identification data.

System and method for tracking bootable devices

A freestanding shelving unit for supporting a first and second foodstuff within a microwave oven having an internal oven compartment with a support surface. The unit includes a generally planar, lower base member and a generally planar, upper platform member. The base member has a top surface for receiving the first foodstuff, a bottom surface receivable on the support surface of the oven compartment, and an outer periphery defining a proximal and a distal edge. The upper platform member has a top surface for receiving the second foodstuff, a bottom surface, and an outer periphery defining a proximal and a distal edge. A yoking portion is provided to extend from a first end supported at the proximal edge of the base member to a second end supporting the upper platform member at its proximal edge a spaced-apart distance from the base member. The upper platform member extends freely from the yoking portion at least partially over the base member.

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Round Rock, TX, United States of America

Michael D Christensen