International Business Machines Corporation

Michael D Amundson

Craig Marshall Darsow

Timothy D Helvey

Joel R Earl

Michael Thomas Repede

David A Lawson

Chin Ngai Sze

Ruchir Puri

Matthew Mantell Ziegler

Brian C Wilson

Dennis Martin Rickert

Dorothy Kucar

Eldon Gale Nelson

A method and apparatus are provided for implementing enhanced physical design quality using historical placement analytics in a design of an integrated gate. Mathematical data analysis is performed to determine placement trends in order to seed an initial placement of subsequent physical design placement processes. A placement seed is generated for a subsequent placement process.

Implementing enhanced physical design quality using historical placement analytics

Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.

Specifying circuit level connectivity during circuit design synthesis

A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Clock alias for timing analysis of an integrated circuit design

A computer implemented method, system and/or computer program product efficiently manage timing parameters in a circuit. Multiple instances of a definition are implemented onto a circuit. A set of related pins from the multiple instances are defined, and a common assertion value is asserted against all pins in the set of related pins.

Efficiently applying a single timing assertion to multiple timing points in a circuit using creating a deffinition

A method, system and computer program product are provided for implementing spare latch placement quality (SLPQ) determination in a floor plan design of an integrated circuit chip. A spare latch placement quality (SLPQ) metric data function is defined and compared to a spare latch placement input with a series of calculations performed. The spare latch placement quality (SLPQ) determination is made based upon the compared SLPQ metric data function and the spare latch placement input. Then associated reports including textual and visual reports are generated responsive to the SLPQ determination. In addition, a new spare latch placement can be constructed with an algorithm responsive to the SLPQ determination.

Implementing spare latch placement quality determination

A system is implemented for controlling long running electronic design automation tools. A user may modify the running of the tool in real time using an interface at the user computer. The user computer accepts user input and communicates with a computer running the design application. The design application runs normally unless a user enters input requiring modification of the process being run by the design application.

Control of design automation process

A method for identifying latches in physical designs with unbalanced slack, comprising: creating a netlist describing a logical design, the logical design having a plurality of latches therein; performing a placement of the logical design to obtain a physical design; measuring a slack difference of each of the plurality of latches; selecting a color for each of the plurality of latches based on the slack difference correspondingly measured for each of the plurality of latches; and generating a graphical image identifying each one of the plurality of latches with slack difference in color, the color selected for each one of the plurality of latches with slack difference being indicative of the severity of the slack difference.

Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization

The present invention provides a method and a computer-readable program for providing generation of graphical congestion images during placement driven synthesis optimization. These graphical congestion images enable a design engineer to make changes and/or improvements to subsequent processes in the design flow before the current placement driven synthesis step completes, thus saving time. This information also provides valuable debug information to PDS developers.

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Oronoco, MN, United States of America

Michael D Amundson