International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Renesas Technology Corp.

Michael Curtis

Raymond Alan Richetta

William Paul Hovis

Adalberto Guillermo Yanes

Steven William Tomashot

Vicki Lynn Pipal

Eric Carpenter

Doug Spannring

Koji Nasu

A method and apparatus for providing high speed, linear-phase interpolation. Signals from a plurality of differential pairs are weighted to produce an output clock having a selectable linear phase variation. A controller includes a pulse generator for providing a predetermined number of pulses having a predetermined phase shift and a predetermined frequency and an interpolator for processing the predetermined number of pulses having a predetermined phase shift and a predetermined frequency to generate a clock signal that is linearly adjustable between a predetermined number of output phases.

Apparatus for providing high speed, linear-phase interpolation

To calibrate the VGA of a read head, test signals from a DAC are input to the VGA and the output of the VGA is observed, with the gain of the VGA being adjusted as appropriate. So that the DAC need not be made with tight tolerances, a DC signal can be fed into the DAC prior to VGA calibration, and an auxiliary ADC is used to receive the output of the DAC and to determine, for a given DC input, what the signal produced by the DAC actually is. In this way, during subsequent VGA calibration the test signal from the DAC is known not by virtue of the DAC having a tight manufacturing tolerance but by virtue of the actual measurements of its outputs for given register inputs.

System and method for providing head amplitude characterization

A packet memory system is provided. The packet memory system includes a memory cell array for storing a predefined number of packets. Each packet includes a predetermined number of segments. Each of the segments defines a starting point of a memory access. A packet decoder coupled to the memory cell array receives packet select inputs for selecting a packet. A segment decoder coupled to the memory cell array receives segment select inputs for selecting a segment. A data flow multiplexer is coupled to the memory cell array for transferring data between a data bus and the memory cell array. Command and mode registers receive command, read/write (R/W) and chip select (CS) inputs for opening a packet. Responsive to an opened packet, the packet select inputs provide a length for the memory access. Each of the segments has a preprogrammed length. Also each of the segments can be defined for a cache line.

Packet memory system

An improved and much simplified method to access data banks in a memory system which provides the option of opening more than one bank in a single command. This is especially useful to achieve bursts of data across bank boundaries in a memory system of synchronous dynamic random access memory cards having fast memory bus speeds. The method decodes signals to generate a single command which may open one or more memory bank at a time. Logic can increment the banks, decrement a bank counter, and, if necessary, increment/decrement a row and/or uniquely address a column so that continual data bursts can be achieved seamlessly across bank boundaries in synchronous dynamic random access memory systems. The data banks may be opened all at once, or can be opened sequentially in a staggered manner according to a synchronous or asynchronous, with respect to the memory clock, time delay During that time delay a nop command or a chip deselect command may execute.

Multiple memory bank command for synchronous DRAMs

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Rochester, MN, United States of America

Michael Curtis