Apple Inc.

Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Michael Couleur

Neil Gibson

Antonio Priego

Nikola Jovanovic

Nicola Rasera

Fabio Ongaro

Siarhei Meliukh

Stefan Herzer

Dashun Xue

Christophe Vaucourt

Andrea Acquas

Bhanupriya Suresh

Shawn Searles

Erich Bayer

Michael Lueders

Joerg Kirchner

Bogdan-Eugen Matei

Frank Trautmann

Syed Wasif Mehdi

Yesim Inam

Ming Sun

Nicola Florio

Pietro Gabriele Gambetta

Giulio Maria Iadicicco

Lei Liao

Nikola Javanovic

The present disclosure describes a system with a first counter circuit, a first converter circuit, a second counter circuit, and a second converter circuit. The first counter circuit is configured to output a first count value based on a comparison between a first reference value and a switched node value of a voltage regulator. The first converter circuit is configured to adjust an activation time of the voltage regulator based on the first count value. The second counter circuit is configured to output a second count value based on a comparison between a second reference value and the switched node value of the voltage regulator. The second converter circuit is configured to adjust an amount of current drawn away from an output of the voltage regulator based on the second count value.

Voltage regulator with pulse frequency control

A multi-level power converter circuit for computer systems maintains phase alignment with other power converter circuits by employing low-gain phase-locked loop circuits. In order to account for different voltage levels on its terminal nodes, the power converter circuit may perform a comparison of the respective voltage levels of its terminal nodes. Using results of the comparison, the power converter circuit can select different regulation modes using different ones of the low-gain phase-locked loop circuits.

Multi-level power converter with low-gain phase-locked loop control

A power converter circuit included in a computer system may employ a compensation loop to adjust the durations of active times during which the power converter circuit sources energy to a load circuit via an inductor. The compensation loop includes an error signal whose value is based on a difference in the output voltage of the power converter circuit from a desired voltage level. During output transients, the error signal is adjusted using an injection current that tracks current flowing through the inductor.

Bias generation for power converter control

Circuitry for bootstrapping and precharging a gate of a field-effect transistor (FET) is disclosed. In one embodiment, an apparatus includes a first transistor coupled to a switching node and further coupled to receive a supply voltage from a supply voltage node, and a second transistor coupled between the switching node and a ground node, wherein the first and second transistors are of a same type. A precharge circuit is configured to precharge a gate terminal of the first transistor to a voltage that is less than a supply voltage on the voltage supply node. The apparatus also includes a bootstrap circuit. Subsequent to precharging the gate terminal of the first transistor, the bootstrap circuit is configured to cause activation of the first transistor by charging the gate terminal to a voltage greater than the supply voltage.

Pre-charging bootstrapped FET gate

A hysteretic current control switching power converter with a clock-controlled switching frequency is disclosed. A power converter includes a switching circuit including a high side switch and a low side switch coupled to one another at a switching node, with an inductor being coupled between the switching node and a regulated supply voltage node. The power converter further includes a control circuit configured to alternately cause activation of the high side switch and the low side switch, wherein the control circuit is configured to activate the low side switch in response to a first voltage reaching peak threshold value, the first voltage corresponding to a current through the inductor. A ramp voltage circuit is configured to, in response to a clock signal, generate a ramp voltage, wherein the peak threshold value is based on the ramp voltage.

Hysteretic current control switching power converter with clock-controlled switching frequency

A power converter is disclosed. The power converter is configured to provide a regulated output voltage. The power converter includes a first control loop configured to generate a first voltage based on a rate of change of the regulated output voltage. A second control loop is configured to generate a second voltage based on an output current provided by the power converter. An amplifier is configured to generate a third voltage based on the first and second voltages. A control circuit is configured to control the regulated output voltage based on the third voltage.

Voltage regulator with dv/dt detection

A control system with a voltage-to-time converter for combined buck-boost converter using a single inductor. The system includes a voltage-to-time converter circuit having first and second inputs coupled to receive first and second voltage signals, respectively. The voltage-to- time converter includes a comparator configured to compare the first voltage signal and the second voltage signal and to generate a comparator output signal at a first level if the first voltage is greater than the second voltage and at a second level if the second voltage is greater than the first voltage. The voltage-to-time converter further includes an output circuit configured to generate first and second output signals based on the comparator output signal. The output circuit is configured to provide a selected one of the first or second output signals at the first level for a duration dependent on a difference between respective voltages of the first and second voltage signals.

Control system with voltage-to-time converter for combined buck-boost converter using a single inductor

A method and apparatus for operating a DC-DC converter in an interleaved (or rotating) pulse frequency modulation (PFM) mode is disclosed. A DC-DC converter includes a number of inductor pairs, with each inductor coupled to a corresponding pulse control circuit. During a cycle in which one of the pulse control circuits sources a current pulse through its respectively coupled inductor, a second pulse control circuit coupled to the other inductor of the pair determines if a voltage on its output node (e.g., where it is coupled to its inductor) is less than a threshold voltage. Responsive to determining that the voltage on its output node is less than the threshold, the second pulse control circuit activates a current path through the other inductor of the pair.

Interleaved pulse frequency modulation mode for a multi-phase buck converter using coupled inductors

A power converter circuit that includes a switch node coupled to a regulated power supply node via an inductor may, during a discharge cycle, sink current from the regulated power supply node. A control circuit may generate the rising and falling ramp signals using voltage levels of an input power supply node and the regulated power supply node. The control circuit may also determine a duration of the discharge cycle using results of comparing respective voltage levels of the generated rising and falling ramp signals.

Phase regulation in a peak current mode power converter

A power converter circuit that includes a switch circuit, and multiple phase and amplifier circuits, may generate a voltage level on a regulated power supply node of a computer system. The amplifier circuits may generate respective demand currents using a voltage level of the regulated power supply node and a reference voltage. In response to activation of a multi-phase operating mode, the switch circuit may short the outputs of the amplifier circuits to generate a common demand current. The multiple phase circuits may sequentially source current to regulated power supply node using the common demand current.

Reconfigurable multi-phase power converter

A power converter circuit included in a computer system may include an adiabatic charge pump which includes multiple capacitors different numbers of which are used to charge and discharge a switch node coupled to regulated power supply node via an inductor. A control circuit may control the dividing ratio of the charge pump circuit as well as determine respective durations of when the charge pump circuit is charging and discharging the switch node.

Regulated power converter with adiabatic charge pump

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. The power converter circuit may generate a reference clock signal using a system clock signal and a voltage level of the switch node. The reference clock signal may be used to initiate a charge cycle, whose duration may be based on generated ramp signals.

Power converter with phase error correction

A DC-DC converter that provides both buck and boost voltages using a single inductor is disclosed. The DC-DC converter includes an H-bridge circuit having an inductor having first and second terminals, and a number of switches. The switches include a first switch coupled between the second inductor terminal and a boost voltage node, a second switch coupled between the second inductor terminal and a buck voltage node, and a third switch coupled between the first inductor terminal and an input voltage node. A control circuit is coupled to activate the switches in accordance with a number of different phases such that a buck voltage (e.g., less than the input voltage) is provided on the buck voltage node, while a boost voltage (e.g., greater than the input voltage) is provided on the boost voltage node.

Combined buck-boost converter using a single inductor

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. During a discharge cycle, the power converter circuit may sense a current being discharge from the regulated power supply node through the inductor into a ground supply node. The power converter circuit may also sense a noise current flowing in the ground supply node, and generate a control current using both the current being discharge and the noise current. Using the control current, the power converter circuit may halt the discharge cycle.

Noise suppression in voltage regulator circuits

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. During a charge cycle, the power converter circuit may generate a reference ramp signal that has an initial voltage level greater than that of the switch node. The power converter may also generate a sense ramp signal using the voltage level of the switch node, and halt the charge cycle using results of a comparison of the respective voltage levels of the reference ramp signal and the sense ramp signal.

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Munich, Germany

Michael Couleur