Intel Corporation

Michael Cornaby

Stephan Jourdan

Stephen H Gunther

Robert J Greiner

Edward Allyn Burton

Anant S Deval

Lawrence O Smith

Francis X Mckeen

Per H Hammarlund

Bryant E Bigbee

Benjamin C Chaffin

Glenn J Hinton

Michael Fetterman

Ronak Signhal

Martin Guy Dixon

Jeremy J Shrall

Michael A Fetterman

Ray Ramadorai

Ben Chaffin

Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Independent power control of processing cores

Methods and apparatus to improve integrated circuit (IC) performance across a range of operating conditions and/or physical constraints are described. In one embodiment, an operating parameter of one or more of processor cores may be adjusted in response to a change in the activity level of processor cores (e.g., the number of active processor cores) and/or a comparison of one or more operating conditions and one or more corresponding threshold values. Other embodiments are also described.

Integrated circuit performance improvement across a range of operating conditions and physical constraints

A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution 'IsoX' mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Mechanism to handle events in a machine with isolated execution

Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.

Vector completion mask handling

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Hillsboro, OR, United States of America

Michael Cornaby