Gte Laboratories Incorporated

Verizon Laboratories Inc.

Other

Intellectual Ventures Ii LLC

Michael Cooperman

Richard W Sieber

Arnold Paige

Nee-Ben Gee

Phillip Andrade

Craig A Armiento

Christopher W Kapral

John Edmund Rathke

Donald J Gray

Albert M Forcucci

Lalit Patel

John Edward Rathke

John W Lovell

William L Geller

Rob Moolenbeek

Arnold H Bearak

Shou-I Wang

D Dean Casey

Philip L Andrade

Craig Armiento

A system () forwards a telephone call to a user. The system () receives a telephone call from a calling party and compares the name of the calling party to a list of names. If the calling party's name matches a name in the list, the system () forwards the telephone call to the user.

Systems and methods for forwarding telephone calls

A method is provided for estimating a number of digital subscriber line nodes ( ) required to supply, from a line supply source ( ), a geographically distributed network of substantially sequentially numbered twisted pair lines with digital subscriber line service. The method comprises the steps of: storing, in number order, data entries for every twisted pair line of the network, each data entry comprising a pair number and a line length of the respective twisted pair line in relation to the line supply source ( ); sorting the entries stored in the database by line length; isolating those sorted entries whose twisted pair lines have a line length greater than a predetermined maximum line length in relation to the line supply source ( ); sorting the isolated entries by number; and discriminating, from the sorted isolated entries, the presence of discrete groupings of substantially contiguous entries.

Method and apparatus for calculating the number of very high speed digital subscriber line nodes

A switch includes input ports, output ports, and merged buffers corresponding to the output ports. Each of the input ports receives cells of a data packet from a source. The output ports output the cells in an order in which they were received by the input ports. The merged buffers temporarily store the cells received by the input ports. Each of the merged buffers includes an output buffer, and input buffer, and a controller. The output buffer stores cells for transmission by a corresponding one of the output ports. The input buffer temporarily stores cells for rerouting to at least one different one of the output ports. The controller reroutes the cells stored in the input buffer to output buffers corresponding to the different output ports.

Distributed control merged buffer ATM switch

Provided herein are methods and systems for providing wide bandwidth using the present twisted pair telephone network. The methods and systems increase the bandwidth of ADSL by statistically sharing the bandwidth of many twisted pair in the neighborhood. An active subscriber would communicate over several twisted pair in the neighborhood, thereby obtaining a dramatic increase in bandwidth.

Broadband architecture using existing twisted pair

This invention relates to the fast reconfiguration of tree switches. In particular, on-chip parallel control signals are time staggered so that they track the propagation of data or information bits. As a result, it is unnecessary to stop the flow of data bits from the data inputs to the data outputs during the reconfiguration of the tree switch.

Tree switching with fast reconfiguration

A distributed switch buffer and method for switch buffer enlargement use standard switch chips as modules that are cascaded in multiples to provide arbitrarily large switch buffers for any number of inputs and outputs. Any type of packet switch chip may be used in any combination. A packet that enters the first switch chip in the cascade automatically gets transferred to other switch chips as part of an integrated buffering scheme. Every input of the switch is connected to all of the switch chips in the first stage of the distributed buffer. The queue of each output of the switch is then expanded by adding more stages of switch chips. All outputs of each switch chip go to the inputs of the same switch chip in the next stage of the distributed buffer so that all of the buffer space of all the cascaded switch chips is available to each input port. The queue may be expanded indefinitely by cascading more chips. In one embodiment, inputs are connected to all the cascaded switch chips for each output port so that each chip only needs to have one output. The number of inputs for each switch chip in the intermediate stages need not equal the number of outputs from that stage, and it is possible to use a different number of cascade stages for each switch output port.

Distributed switch buffer utilizing cascaded modular switch chips

A signal switch with merged buffer architecture has multiple input ports connected to a circuit switch matrix which partially sorts the input signals based on output port destination. The circuit switch matrix is connected to multiple merged buffers, each in turn connected to a corresponding output port and feedback. Input signals entering the circuit switch matrix are normally sent to the buffer attached to the destination output port of the input signal, but, if more than one input signal is contending for an output port, all but the first contending input signal are misrouted to merged buffers that are not busy. The location in memory of all of the correctly routed and misrouted input signals in the switch is tracked by a control, which also routes input signals to their output port destinations from the merged buffers, and reroutes misrouted input signals to the correct buffers. The control does not reroute a misrouted signal until its intended buffer is no longer busy, so that each input signal is rerouted at most once. The control can also track the priority, sequence number, and output port destination of each input signal, in order to give preference to the higher priority input signals going to a particular output port. Buffer overflow can be minimized and switch resources more efficiently utilized by denying rerouted input signals access to a output buffer until the number of cells potentially waiting in that output buffer has dropped below a predetermined threshold. Buffer usage is balanced across the switch by changing the order in which buffers receive misrouted input signals. At the onset of congestion, signals are discarded when necessary at predetermined priority-dependent buffer signal occupancy thresholds. Multicasting can be handled by initially treating a multicast signal as a misrouted signal. The multicast signal is first routed to a merged buffer which did not receive a correctly routed signal, then it is rerouted simultaneously to all of the merged buffers corresponding to its output port destinations, so that all signals can be then sent to the appropriate output ports during a subsequent time period.

Merged buffer signal switch

A switching matrix routes each received input to a unique output port. Each input specifies an output port as a destination. For each output port, a set of inputs contending for the output port is determined. A control for correctly routing selects an input from each set of contending inputs and routes it to the correct output port of the switching matrix. If no input specifies an output port as a destination, that output port is designated as an available output port. A control for misrouting determines the set of available output ports and the set of inputs that have not been correctly routed by the control for correctly routing. The control for misrouting then misroutes each remaining input to one of the available output ports of the switching matrix. The switching matrix may provide status signals for use by the switch in tracking the location of the correctly routed and misrouted inputs.

Switching matrix with contention arbitration

An apparatus and method for push-out of signals from switch buffers ensures that a high percentage of the highest priority input signals are accepted by the switch by using the switch resources to remove lower priority input signals from the switch buffer in order to accommodate higher priority input signals. Signals of any priority may be pushed out of the switch buffer. The apparatus requires a queue with simultaneous read and write capability and a switch that performs one read operation to N write operations, N being the number of input ports. It pushes signals out of the buffer by performing additional 'dummy' read operations to read out signals of the specified priority, and then discards the signals by preventing them from entering the parallel-to-serial shift registers. A preferred embodiment of the invention utilizes an ATM CAM-controlled switch fabric, where the CAM receives the arrival number and priority of each cell in the buffer. The location of low priority cells is found by activating a dummy read priority line and addressing the CAM.

Push-out of low priority signals from switch buffers

An asynchronous transmission mode (ATM) memory array capable of storing one ATM packet of data is an n x m array of memory locations, each memory location capable of storing one bit. The array has n columns, where n is the number of bits in an ATM cell of data, and m rows, where m is the number of cells in an ATM packet. The memory array has a plurality of input lines, one for each of said n columns, which together receive n bits simultaneously. It also has n ground lines, one for each of said n columns in said array, each ground line connected to one memory location in each of said n columns in its row; such that each ground line carries the current of only one bit, thereby reducing the noise transients.

ATM memory with reduced noise transient

An asynchronous transfer mode switch with shared memory under the control of a content addressable memory, receives serially through a plurality of input ports a plurality of cells of digital data packets during a specific time period, each packet having a header. The header of each said cell is processed and temporarily stored. The data bits of each cell are temporarily stored, and transferred in parallel to a random access memory, using available addresses in said random access memory. A header processor assigns an arrival number to each received cell, and extracts the output port destination and priority of each cell from said headers. A content addressable memory stores the arrival number, output destination port and priority of each data cell. A read control provides sequentially, in order of priority, arrival numbers, and destination addresses, to said content addressable memory for determining the order in which cells of data are read from said random access memory. When a match is found in said content addressable memory, the cell of data from the associated address in said random access is read out to its output destination port under control of said content addressable memory.

ATM shared memory switch with content addressing

An Asynchronous Transfer Mode (ATM) cell alignment assembly aligns an incoming ATM cell within an internal time slot of an ATM matrix by controllably time-delaying the cell before being switched by the matrix. The alignment assembly includes a 53-byte-wide shift register having a serial input receiving the incoming ATM cell, and fifty-three parallel outputs each coupled to a respective input of a 53.times.8 programmable crosspoint switching array. Each output of the array is coupled to an input of a shift register having eight parallel inputs and a serial output coupled to a respective input of the ATM matrix. The crosspoint switching array establishes only a single selected switching path through the array in accordance with the desired time delay, and is reconfigured upon the arrival of each incoming ATM cell.

Method and apparatus for ATM cell alignment

A broadband space switch matrix includes a parallel combination of individual switch modules each comprising a cascade of pass-transistor selectors, NAND gates, and inverters arranged into a multi-stage tree multiplexing configuration. The switching speed is increased by isolating each switching crosspoint from the stray capacitive loading in the matrix.

Broadband switch

Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The ECL input is applied to the gate of the N-type transistor of the first inverter circuit. A threshold control circuit includes a CMOS inverter circuit with the gate of the N-type transistor connected to a reference voltage and the gate of the P-type transistor connected to its drain is connected to the gate of the P-type transistor of the first inverter circuit. The threshold control circuit adjusts the threshold voltage of the first inverter circuit so as to compensate for changes in current flow through the N-type or P-type transistors, thereby permitting operation over extreme variations in circuit parameters under situations of poor operating tolerances and wide temperature variations.

Electrical circuitry with threshold control

Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The MOS transistors of the first inverter circuit of the series are approximately three times larger than the MOS transistors of the same type in subsequent inverter circuits of the series. The ECL input is to the gate of the N-type transistor of the first inverter circuit. A threshold control input is connected to the gate of the P-type transistor of the first inverter circuit. This configuration increases the operating speed of the first inverter circuit and permits controlling the threshold voltage in order to stabilize the output duty cycle.

Growing community of inventors

Framingham, MA, United States of America

Michael Cooperman