Intel Corporation

Michael Christenson

Nafees Kabir

Noriyuki Sato

Hui Jae Yoo

Matthew V Metz

Kevin Lai Lin

Elijah V Karpov

Manish Chandhok

Christopher J Jezewski

James M Blackwell

Ramanan Chebiam

Carl H Naylor

Miriam Ruth Reshotko

Tristan A Tronic

Jeffery D Bielefeld

Jiun-Ruey Chen

Colin T Carver

Richard F Vreeland

William Brezinski

Sasikanth Manipatruni

Ian A Young

Tanay Gosavi

Kaan Oguz

Kevin O'Brien

Christopher J Wiegand

Angeline Smith

Tofizur Rahman

Benjamin Buford

Rohan Patil

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Subtractively patterned interconnect structures for integrated circuits

Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

Methods and structures for improved electrical contact between bonded integrated circuit interfaces

A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

Two terminal spin orbit memory devices and methods of fabrication

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Hillsboro, OR, United States of America

Michael Christenson