Samsung Electronics Co., Ltd.

Yonsei University

Korea Advanced Institute of Science and Technology

Sogang University Corporation

Michael Choi

Youngjae Cho

Kyung-Hoon Lee

Jungho Lee

Eun Seok Shin

Jung-ho Lee

Sungno Lee

Kyoungjun Moon

Yong-Woo Kim

Hyochul Shin

Dongryeol Oh

Sang-Pil Nam

Younghyo Park

Heejune Lee

Jinwoo Park

Kwangho Kim

Jung Ho Lee

Sangheon Lee

Taewan Kim

Yongjin Lee

Kyunghoon Lee

Sang-Heon Lee

Sangho Kim

Choong-Hoon Lee

Yongki Lee

Eunhye Oh

Jooseong Kim

Kyung-hoon Lee

Eun-seok Shin

Junhee Shin

Heechang Hwang

Sung-Sang Lim

Sangpil Nam

Seungyeob Baek

Seung Yeob Baek

Hyungyu Kim

Byungwoo Koo

Sunghan Do

Jung Hoon Lee

Kyung Min Kim

Seung-hoon Lee

Seunghoon Lee

Miyoung Kim

Young-Ju Kim

Kyung Hoon Lee

Youngjoo Lee

Bumsoo Kim

Yoonkyung Choi

Jungho Kim

Jinchul Lee

San-ho Byun

Seung-Tak Ryu

Taewook Kim

Jae Cheol Yun

Byung-Wook Min

Junchul Park

Yongwoo Kim

Ho Jin Park

Chadong Kim

Jae-Cheol Yun

Hyungdong Roh

Junsang Park

Jaekeun Lee

Sin Hwan Lim

Sin-hwan Lim

Hyungjong Ko

Jounghyun Yim

Hyunwoong Lim

Hojin Park

Hyunkyu Ouh

Hae Sick Sul

Sanghyub Kang

Hae-sick Sul

Marutha Muthu Muthuveeran

Ho-jin Park

Kyoung-jun Moon

Se-won Lee

Beom-soo Park

Ilhoon Jang

Min-Jae Seo

Seongsoo Park

Jooik Chung

Dongsuk Lee

Il Hoon Jang

Sera An

Chanhui Park

Kiryong Song

Bosung Suh

Hyung Dong Roh

Woongtaek Lim

Heewook Shin

Yong-min Kim

An attenuator includes: a first transmission line connected between a first terminal and a first node; a second transmission line connected between the first node and a second terminal; a first resistor connected between the first terminal and a ground node; a second resistor connected between the second terminal and the ground node; and a third resistor connected between the first node and the ground node, wherein the first and second resistors each have a resistance that is higher than a resistance of the third resistor.

Attenuator including nonuniform resistors and apparatus including the same

A frequency multiplier includes a capacitor circuit having a plurality of capacitors therein, and is responsive to a differential input signal applied to an inverting input node and a non-inverting input node thereof. A frequency multiplication circuit (FMC) is provided, which has a plurality of transistors therein. The FMC is configured to receive components of the differential input signal passing through the plurality of capacitors, and multiply a frequency of the components of the differential input signal. A plurality of inductor loads are provided, which are connected to an inverting output node and a non-inverting output node of the FMC, and are configured to convert a current signal generated by the FMC into a voltage signal.

Frequency multiplier circuits having cross-coupled capacitors therein which support frequency multiplication

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

Built-in self-test circuit and temperature measurement circuit including the same

A monitoring circuit includes a sensor circuit having a plurality of devices and a selection circuit, which selects a device to be monitored among the plurality of devices, an input circuit, which applies, based on input digital data, a first signal to the device to be monitored and an output circuit, which generates output digital data based on a second signal generated by the sensor circuit. The input circuit includes a digital-to-analog converter, and the output circuit includes an analog-to-digital converter.

Monitoring circuit, integrated circuit including the same, and operating method of monitoring circuit

An apparatus configured to transmit and receive a radio frequency (RF) signal is provided. The apparatus includes a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal, a power amplifier configured to amplify the analog signal, and an antenna configured to output, as the RF signal, the amplified analog signal to the outside. The DAC includes a current cell matrix including a plurality of current cells configured to generate the analog signal, a plurality of normal paths configured to control the plurality of current cells to be turned on or off, based on the digital signal, and a plurality of alternative paths configured to selectively consume power, based on a pattern of the digital signal.

Digital-to-analog converter and apparatus including the same

A digital droop detector for detecting whether a droop occurs in a power supply voltage, may include processing circuitry configured to, detect a voltage level change of a power supply voltage in response to a clock signal, the detecting the voltage level change including converting the detected voltage level change into a first code, correct at least one nonlinearity included in the first code, the correcting including converting the first code into a second code and a target range, and adjust a delay magnitude of the clock signal based on the second code.

Digital droop detector, semiconductor device including the same, and calibration method thereof

An analog-to-digital conversion circuit includes analog-to-digital converters (ADCs) including a target analog-to-digital converter (ADC) providing second data samples, a first adjacent ADC providing first data samples, and a second adjacent ADC providing third data samples. The ADCs perform an analog-to-digital conversion using a time-interleaving approach in response to clock signals having different phases and including a reference clock signal. A timing calibration circuit includes a relative time skew generator generating a relative time skew and an absolute time skew generator generate an absolute time skew. A clock generator adjusts at least one phase of the clock signals based on the absolute time skew.

Analog-to-digital conversion circuit and receiver including same

A multiplexer includes a charging circuit; a plurality of sampling switches receiving a plurality of input signals; and a plurality of boosting circuits connected between the sampling switches and the charging circuit and sharing the charging circuit. First and second charging switches of the charging circuit are controlled by a first clock signal. Each of the boosting circuits includes a first boosting switch connected to a first node of the charging circuit and a gate of one of the sampling switches, a second boosting switch connected between a second node of the charging circuit and the one sampling switch, and a level shifter configured to control the first boosting switch and the second boosting switch in response to a second clock signal and a selection signal.

Multiplexer and semiconductor device including the same

A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.

Built-in self-test circuits and semiconductor integrated circuits including the same

An analog-to-digital conversion circuit includes; a first analog-to-digital converter (ADC), a second ADC and a third ADC collectively configured to perform conversion operations according to a time-interleaving technique, and a timing calibration circuit configured to calculate correlation values and determine differences between the correlation values using first samples generated by the first ADC, second samples generated by the second ADC, and third samples generated by the third ADC during sampling periods, wherein the timing calibration circuit is further configured to control a phase of a clock signal applied to the second ADC in response to a change in absolute value related to the differences generated during the sampling periods.

A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

Semiconductor integrated circuit and method of testing the same

An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.

Analog-to-digital converter

An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

A flicker detection circuit is provided. The flicker detection circuit may include a flicker detection correlated double sampling (FD CDS) circuit including first to sixth switches turned on or off based on a control signal, and first to fourth capacitors, the FD CDS circuit being configured to receive a flicker pixel signal output from at least one pixel, summate with an output offset signal, and amplify the summation based on a gain to form a flicker detection signal; and an analog-to-digital converter (ADC) configured to quantize the flicker detection signal.

Correlated double sampling circuit and image sensor including the same

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Seoul, South Korea

Michael Choi