Lsi Logic Corporation

Mitsubishi Electric Research Laboratories, Inc.

Michael Casey

Paris Smaragdis

Hong Hao

A system and method are provided for accelerating development and debug of a printed circuit board (PCB) designed for use with a platform ASIC in advance of availability of a prototype sample of the platform ASIC. Aspects of the invention include a pin-out adapter card that implements a predefined pin-out of the ASIC and that hosts FPGA logic resources for emulating I/O functionality and some (or all) of the ASIC core logic; a PCB designed for use with the platform ASIC, wherein the PCB includes the predefined ASIC pin-out for eventually mating with the ASIC; and a socket having mating connectors on both sides for mating with the ASIC pin-out on the PCB and to the ASIC pin-out on the adapter card, respectively, for coupling the adapter card to the PCB, thereby enabling development and debug of the PCB prior to availability of ASIC samples.

Accelerating PCB development and debug in advance of platform ASIC prototype samples

A method detects objects in a scene over time. Sets of time-aligned features are extracted from multiple signals representing a scene over time; each signal is acquired using a different modality. Each set of time-aligned features is arranged as a vector in a matrix to which a first transform is applied to produce a compressed matrix. A second transform is applied to the compressed matrix to extract spatio-temporal profiles of objects occurring in the scene.

Detecting temporally related components of multi-modal signals

The invention provides a system and method for providing scalability in an integrated circuit (IC) having a package coupled to a die through package balls. The die includes a plurality of input/output (I/O) slots and a hardmac configured to implement a logic function. A patch board is included between the hardmac and the I/O slots, wherein the hardmac includes a plurality of attachment points. The hardmac is attached to the plurality of I/O slots through the patch board, wherein adjacent attachment points join to non-adjacent I/O slots through the patch board.

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London, United Kingdom

Michael Casey