Intel Corporation

Michael Calyer

Narayan Biswal

Seh Kwa

Ravi Ranganathan

Paul S Diefenbaugh

Barnes Cooper

Inder M Sodhi

Andrew D Henroid

Faraz A Siddiqi

Ruchika Singh

In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.

Rescheduling workloads to enforce and maintain a duty cycle

Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.

Techniques to control self refresh display functionality

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San Jose, CA, United States of America

Michael Calyer