Freescale Semiconductor,inc.

Motorola Corporation

Michael C Wood

James M Sibigtroth

George E Baker

James Robert Feddeler

George L Espinor

Michael W Rhoades

Daniel Mark Thompson

Linda R Nuckolls

Bruce L Morton

Jay A Hartvigsen

Edward J Hathaway

Stephen Pickering

William Edward Getka

William L Lucas

Christian Vetterli

Greg A Racino

Edward M Stellini

Timothy E Barnard

A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.

Memory management unit and method of accessing an address

Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Data transfer coherency device and methods thereof

Coherent access register data transfer device and methods thereof

A low voltage detection (LVD) system for a logic device includes a first LVD circuit () to provide an indicator when a supply pin voltage () falls below a first voltage level, and a second LVD circuit () to provide an interrupt () when the supply pin voltage falls below a second voltage level. In one embodiment, the second LVD circuit consumes more power than the first LVD circuit, and is therefore selectively enabled. In one embodiment, when the supply pin voltage is between the first and second voltage levels and the logic device is in a stop or low power mode, the second LVD circuit is periodically enabled to monitor the supply pin voltage. After the supply pin voltage falls below the second voltage level, the logic device is placed in a safe state where the logic device is inhibited from acknowledging interrupts until the supply pin voltage rises above the first voltage level.

Low voltage detection system

A data processing system () has an embedded non-volatile memory () that is programmed and erased by use of a high voltage provided by a charge pump (). In order to prevent the non-volatile memory () from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump () is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit () in response to a program or erase operation being initiated. A control register () will provide a high voltage enable signal to the charge pump () only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit () may be enabled by another condition to protect the data processing system () from an authorized access.

Method and apparatus for protecting an integrated circuit from erroneous operation

Embodiments of the present invention relate to a mechanism to prevent the oscillator from being stopped when a host development system is coupled to the background debug communications interface and the background debug mode has been enabled. This allows background debugging operations to continue when the target data processing system is in a low power mode. Other embodiments relate to a mechanism for allowing a host development system to request a synchronization timing pulse from a target data processing system so the correct clock speed can be determined for background communications. Alternate embodiments relate to a data processing system having a system clock unit and a background debug system where the background debug system includes a background debug clock unit, separate from the system clock unit, and an enable control. When the enable control is asserted, the background debug clock unit is enabled, independent of the system clock unit.

Data processing system having an on-chip background debug system and method therefor

A debug module ( ) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory ( ) during program development. The debug information is provided to an external host via a serial communication interface ( ) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.

Data processing system with on-chip FIFO for storing debug information and method therefor

A system comprising a supply voltage isolation module ( ), and a battery detector ( ), both responsive to a battery pin ( ). The system further including a voltage detection module ( ) responsive to a voltage supply pin ( ), where the voltage detection module ( ) compares a supply voltage from the voltage supply pin ( ) to a threshold. The system also including control logic ( ) responsive to the battery detector ( ) and the voltage detection module ( ). Also disclosed are methods for responding to connection of a battery ( ) to a logic device ( ), placing a logic device ( ) into a low power state in response to connection of a battery ( ) to the logic device ( ), and detecting a battery condition for a logic device ( ) having a battery pin ( ).

Methods and systems for detecting and for responding to connection of a battery to a logic device

An integrated circuit containing a data processing system with a number of external peripheral pins utilizes the peripheral pins for both testing the corresponding peripherals and for parallel testing of other complex functions in a MCU. The MCU has a plurality of test modes that can be selected, with different peripheral pins being connected to a test circuit depending on which test mode is selected. This allows testing of peripherals via their corresponding pins, as well as other complex functions without the necessity of having dedicated test pins.

Data processing system external pin connectivity to complex functions

A method for automatically detecting a programmed status of a non-volatile memory and selecting one of multiple operational modes based on that status. In one embodiment a non-volatile memory (102) has a normal and an access restricted operational mode. The memory is placed in the access restricted operational mode once it is programmed in order to prevent unauthorized access to the programmed data. A detection logic (226) determines whether the non-volatile memory is in a non-programmed state. Based on this detection it is determined whether the non-volatile memory is to be placed in a normal or an access restricted operational mode. The invention relates also to determining an operational mode of the microcontroller which can advantageously be incorporated into an assembled electronic device.

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Pflugerville, TX, United States of America

Michael C Wood