International Business Machines Corporation

Michael C Triplett

Steven M Shank

Dale Warner Martin

Mousa H Ishaq

Timothy S Hayes

Deborah A Tucker

Marshall J Fleming, Jr

Casey Jon Grant

Heidi L Greer

Michael Raymond Lunn

Charles Augustus Choate, Iv

Dean W Siegel

Paul R Nisson

A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Method to eliminate arsenic contamination in trench capacitors

A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

Gate stacks

A method and structure for fabricating semiconductor wafers. The method comprises providing a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A material is chosen from the plurality of materials existing in the relationship. A substructure is formed comprising the material sandwiched between a topside of the first semiconductor wafer and a backside of a portion of the of the second semiconductor wafer. The plurality of semiconductor wafers are placed into a furnace comprising an elevated temperature for processing resulting in a value for the first semiconductor wafer of the electrical characteristic that corresponds to said material in said relationship.

Modification of electrical properties for semiconductor wafers

A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.

A method evaluating an integrated circuit manufacturing process first establishes a 'desired' profile of a given film in a prescribed manufacturing process by first recording multiple thickness measures taken at regular intervals along a number of lines crossing a plurality of different sample production runs of the same film formed in the integrated circuit manufacturing process. Next, the invention plots the thickness measures to produce sample film profiles of the film. These sample film profiles are averaged in a statistical process to produce the desired film profile. The desired film profile is compared to an actual production run. If the actual film profile does not match the desired film profile, the integrated circuit manufacturing process used to make the actual film profile can then be adjusted to make the actual film profile match the desired film profile more closely.

Methodology for measuring and controlling film thickness profiles

The present invention describes a method of forming a thin film on a substrate arranged in a deposition system comprising the step of introducing a pre-determined amount of an impurity in a confined volume in the deposition system. One or more gases are introduced into the deposition system for forming the thin film. The impurity is removed from the confined volume in a gas phase during formation of the thin film. The impurity in the gas phase is incorporated into the thin film.

Growing community of inventors

Colchester, VT, United States of America

Michael C Triplett