Vanguard International Semiconductor Corporation

Alliance Semiconductor Corporation

Cypress Semiconductor Corporation

Other

Michael C Stephens, Jr

Luigi Ternullo, Jr

David V James

Jagadeesan Rajamanickam

Jeffrey Scott Earl

Ajit K Medhekar

Christopher Ematrudo

Chitranjan N Reddy

Sanjay M Wanzakhade

Kenneth A Poteet

Sanlay M Wanzakhade

Michael F Vincent

According to an embodiment, a content addressable memory (CAM) device () may be capable of executing a 'restricted' search operation. A restricted search operation (an 'explore' or &#x201c;search beyond&#x201d; operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.

Method and apparatus for restricted search operation in content addressable memory (CAM) devices

A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. The CBC receives a control signal that is used to dynamically configure the chip into an operational mode, as well as the VLD signal. In response to the control signal, the switch threshold of the CBC is configured to a predetermined level corresponding to the selected operational mode. The predetermined trip point causes the CBC to appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by the configured operational mode. One embodiment of the CBC uses a configurable pull-up circuit to alter its switch threshold or trip point. The configurable pull-up circuit is used to pull-up the voltage at an intermediate node that is buffered and propagated to the on-chip voltage generator to activate and de-activate the voltage generator. The configurable pull-up circuit more strongly pulls up this voltage in one operational mode compared to another operational mode to alter the switch threshold.

Dynamically adjustable on-chip supply voltage generation

A content addressable memory (CAM) device () may include a number of sub-blocks (-to-) that can generate CAM search results. In a 'search beyond' operation, sub-blocks (-to-) may be excluded from a search operation according to criteria, including a sub-block address and a soft-priority value. A CAM device may include a compare circuit () that may compare sub-block address values in a time division multiplexed fashion to establish priority from among multiple CAM sub-blocks.

Compare circuit and method for content addressable memory (CAM) device

According to one embodiment, a search engine device () may include an input (), search portion (), and a vote portion (). A vote portion () may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion () may generate an output response having its own precedence information.

Search engine device and method for generating output search responses from multiple input search responses

A content addressable memory (CAM) device () may include a number of blocks (-[11]) that each generate CAM search results and result compare circuits (-[11] that receive CAM search results from multiple blocks (-[11]), and compare at least a portion of such CAM search results. According to such a comparison result, a compare circuit (-[11]) can generate an output CAM search result for subsequent comparison with CAM search result in another compare circuit (-[&#x2212;11]).

Result compare circuit and method for content addressable memory (CAM) device

A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The current through a first MOS transistor is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source is connected to a reference voltage. The first MOS transistor has the standard threshold implantation but not the threshold voltage reticle option. The current through a second MOS transistor is measured by forcing the same test voltage on the drain and the gate. The gate and said drain of the second MOS transistor are connected together while the source is connected to a reference voltage. The second MOS transistor has the standard threshold voltage implantation and the threshold voltage implantation reticle option layer. The current through the first NMOS transistor and the current through the second MOS transistor are compared to detect the presence of the threshold voltage implantation reticle option layer in the integrated circuit device.

Reticle option layer detection method

A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., &frac18;, &frac14;, &frac12;, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of &frac18;th of the self-refresh cycle, the activation of the second most significant bit signals completion of &frac14;th of the self-refresh cycle, the activation of the most significant bit signals completion of &frac12; of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.

Self-refresh test time reduction scheme

A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high. The logic circuit can also vary the voltage difference between the capacitor node and the external supply voltage to decrease the relative voltage level at the capacitor node relative to the level of the external supply voltage. These features also help reduce the risk of junction breakdown in the charge pump.

Internal charge pump voltage limit control

A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.

Multiple data clock activation with programmable delay for use in

A regulator system for an on-chip-generated supply voltage includes a voltage detection circuit, a power-up mode detection circuit, a normal mode detection path, and a power-up detection path. The voltage detection circuit monitors the on-chip-generated supply voltage and generates a signal that indicates the level of this supply voltage. The power-up mode detection circuit detects when the chip is in the power-up mode and generates a path select signal. The path select signal causes the regulator system to select the power-up detection path during the power-up mode and to select the normal detection path when not in the power-up mode. The power-up detection path includes voltage regulation circuitry that does not rely on a reference voltage. In one embodiment, the power-up detection path includes a logic gate coupled to receive the signal from the voltage detector. The logic gate is skewed to have a trip point that corresponds to voltage level slightly greater than that of the external supply voltage. The logic gate controls the on-chip voltage generator to maintain the on-chip-generated voltage level at a magnitude greater than that of the external supply voltage. During power-up, the power-up detection circuit selects the power-up detection path, thereby avoiding the need to disable the on-chip voltage generator as in conventional systems that depend on a reference voltage.

On-chip-generated supply voltage regulator with power-up mode

The present invention provides a method and apparatus that accomplishes a high performance, random read/write SDRAM design by synchronizing the read and write operations at the data line sense amplifier. This enables the design to perform random read and write operations without varying cycle time issues or unbalanced margin issues. The data lines are used as bi-directional lines to accomplish high performance reads and writes with minimal additional wiring overhead required. During a read operation, read data is transferred from the memory cells of the device across a series of consecutive pairs of data lines to an input/output port of the memory device. The first pair of data lines is coupled to a data line sense amplifier. The additional pairs of data lines are coupled to additional amplifiers. During a read operation, data is transferred across the consecutive pairs of data lines according to the timing cycles of the respective amplifiers. In order to quickly drive the data signals during a write operation up the series of consecutive pairs of data lines, the timing signals for each of the pairs of data lines except the first pair of data lines are disabled so that the data lines are allowed to float, and then the data lines are overdriven with the write data so that the write data quickly transitions up the series of data lines to the selected data line sense amplifier, where it arrives at approximately the same time that read data normally arrives during the timing cycle for the data line sense amplifier.

High-speed synchronous write control scheme

A mock wordline timing scheme is used in a memory device having a plurality of memory cells arranged in array blocks. The array blocks are further arranged in groups, with each array block being located between a pair of corresponding sense amplifier banks. Each array block has at least one mock wordline, and each sense amplifier bank is shared by the array blocks located on either side of the sense amplifier bank, except the sense amplifier banks located on the ends of the group of array blocks. Each sense amplifier bank has a corresponding sense timing control circuit coupled to receive an enable signal and a timing signal. In response to an address, a row decoder is configured to be selected to drive the addressed word line. In conjunction with the row decoder, the enable and timing signals of the sense amplifier bank adjacent to the array block containing the addressed memory cell are asserted. The row decoder causes the timing signal to be propagated through a mock wordline that is not in the same array block as the addressed memory cell. Thus, memory cells in the active array are not disturbed, which could result in incorrect sensing and data corruption. Further, unlike some conventional schemes, the selected mock wordline is in an inactive array block even if the active array block is at an end of the bank of array blocks.

Mock wordline scheme for timing control

A regulator system includes first and second voltage sensing circuits coupled to a voltage generator control circuit. The first and second voltage sensing circuits are configured to monitor the voltage generated by the on-chip voltage generator (i.e., the on-chip supply voltage) and detect when the on-chip supply voltage reaches thresholds that are predetermined to define a desired range of the on-chip supply voltage. The voltage generator control circuit receives voltage sense signals from the voltage sense circuits and, in response, asserts or de-asserts a control signal received by the on-chip voltage generator so as to activate or de-activate the on-chip voltage generator to maintain the on-chip supply voltage within the desired range. The voltage generator control circuit introduces hysteresis in the generation of the control signal provided to the on-chip voltage generator. As a result of this hysteresis, once the on-chip voltage generator is activated, the voltage generator control circuit only de-activates the on-chip voltage generator when the on-chip supply voltage reaches the higher threshold. Conversely, once the on-chip voltage generator is de-activated, the voltage generator control circuit only activates the on-chip voltage generator when the on-chip supply voltage reaches the lower threshold.

Regulator system for an on-chip supply voltage generator

An activation arrangement for reducing worst case localized supply noise for shared circuitry includes a first group of circuit blocks, a second group of circuit blocks, a shared circuit, and a selection circuit. The first and second circuit blocks are arranged symmetrically about the shared circuit. The selection circuit is configured to selectively activate each circuit block in the first group and, concurrently, a circuit block in the second group corresponding to the circuit block of the first group. The selection circuit is configured so that when the circuit block of the first group that is closest to the shared circuit is to be activated, the corresponding circuit block in the second group is the circuit block that is farthest from the shared circuit. In a similar manner, the selection circuit is configured so that when the circuit block in the first group that is second closest to the shared circuit is to be activated, the corresponding circuit block in the second group is the circuit block that is second farthest from the shared circuit, and so on.

Distributed array activation arrangement

A semiconductor memory device with a pair of data lines for reading and writing data signals to and from a matrix of memory cells and an accelerator circuit for accelerating the generation of a data signal on at least one of the data lines is disclosed. Slow signal generation on the data lines is due to the characteristics of NFET pass gates passing high signals, or PFET pass gates passing low signals. In an implementation using NFET pass gates, the accelerator circuit includes a pair of cross-coupled PFET transistors, one of which is activated by the low signal on the opposing data line. The drains of the cross-coupled PFET transistors are coupled to the data lines, such that when the low signal on the opposing data line activates one of the PFETs, it supplies additional current to the data line receiving the high signal, so as to accelerate the generation of the high signal on the data line. Faster signal generation allows for the data line latches of the circuit to be set earlier, thus allowing the read cycle of the memory device to be faster. An additional result of the increased signal generation on the data line that is receiving a high signal is that at the end of the cycle when the two data lines are coupled together, their average voltage due to charge sharing tends to be closer to a desired midlevel voltage such that less power is required to bring the two data lines to the desired mid-level voltage at the end of the signal cycle.

Growing community of inventors

San Jose, CA, United States of America

Michael C Stephens, Jr