Texas Instruments Corporation

Michael C Stephens, Jr

Duy-Loan T Le

Scott E Smith

Roger D Norwood

Masayoshi Nomura

Kenneth A Poteet

Vipul C Patel

Charles J Pilch

Terry T Tsai

Arthur R Piejko

An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.

Output buffer with boost from voltage supplies

A method and apparatus for testing the self-refresh operation of a dynamic memory part are provided in which an oscillator (140) is coupled to a self-refresh counter (142). The self-refresh counter (142) causes a refresh row address counter (144) to generate row addresses for self-refresh cycles. The refresh row address counter (144) is coupled to a self-refresh control circuit (148). The self-refresh control circuit (148) is operable to generate a signal indicating completion of a self-refresh cycle. The refresh row address counter (144) is also coupled to a multiplexer (146). The multiplexer (146) outputs row addresses from either the refresh row address counter (144) or those supplied externally for rows to be refreshed.

Method and apparatus for production testing of self-refresh operations

A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) generate column addresses for each memory section based on a starting address, thereby allowing for internal operation at less than the external system frequency. An operation mode register (29) stores mode data for controlling certain operations, and a state machine (130) operates to prevent indeterminate operation if invalid mode data is input to the operation mode register (29).

Method and apparatus for preventing invalid operating modes and an

Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.

Dual receiver edge-triggered digital signal level detection system

The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements. When activated for redundancy, the second level redundancy scheme replaces at least one defective sub-block of memory devices with a like number of redundant sub-blocks of memory devices.

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Stafford, TX, United States of America

Michael C Stephens, Jr