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Los Gatos, CA, United States of America

Michael C Stephens, Jr

Average Co-Inventor Count = 1.00

ph-index = 7

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 167

Michael C Stephens, JrMichael C Stephens, Jr (33 patents)
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Inventor’s number of patents
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Strength of working relationships

Company Filing History:

1. Other (17 from 832,718 patents)

2. Iii Holdings 2, LLC (16 from 88 patents)


33 patents:

1. 11935578 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

2. 11398267 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

3. 10923176 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

4. 10497425 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

5. 10199087 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

6. 9906218 - Dual-gate transistor control based on calibration circuitry

7. 9806708 - Reference level adjustment for calibration of dual-gate transistors

8. 9659628 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

9. 9601167 - Semiconductor device having dual-gate transistors and calibration circuitry

10. 9510176 - Portable device emergency beacon

11. 9455001 - Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array

12. 9424888 - Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

13. 9344080 - Dual-gate transistor control based on calibration circuitry

14. 9304525 - Reference level adjustment for calibration of dual-gate transistors

15. 9286955 - Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array

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as of
12/12/2025
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