Analog Devices,inc.

Michael C St Germain

Kimo Tam

Mohammad Hassan Ghaed

Kimo Y F Tam

John G Kenney

Jennifer Lloyd

Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Multiphase clock generators with digital calibration

Various examples are directed to systems and methods for providing correction to cascaded signal components. A correction signal may be applied to multiple signal components in a set of cascaded signal components.

Parameter correction for cascaded signal components

Various examples are directed to crosspoint switches and methods of use thereof. An example cross point switch comprises a first row buffer, a second row buffer, a first column buffer, and a second column buffer. The crosspoint switch may also comprise a first switch that, when closed, electrically couples the second row buffer to the first column buffer, and a correction controller. The correction controller may be configured to send a first correction signal to the first row buffer; send a second correction signal to the second row buffer; receive an indication that the first switch is closed; send a third correction signal to the first column buffer; and send a fourth correction signal to the second column buffer.

A crosspoint switch matrix may include a plurality of point cells provided at intersections between a plurality of input pathways and a plurality of output pathways. The input pathways may be partitioned into groups, each group defined by a demultiplexer that forwards an input signal to the point cells within the group and/or to a demultiplexer of a succeeding group. The output pathways may be partitioned into groups, each group defined by a multiplexer that forwards a signal from an active point cell to an output of the matrix. Multiplexers of groups in intermediate positions between the point cell and the matrix output may relay the output signal between the multiplexers along a bypass pass. When both the input pathways and output pathways are so partitioned, each point cell may be a member of one input pathway group and one output pathway group.

Scalable crosspoint switch

Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.

Apparatus and method for equalization

An impedance matched lane reversal switching system including first and second transceiver pairs, each of the pairs including a transmitter connected to a receiver, the output of the transmitter connected to the input of the receiver and to a node, the node of each pair interconnected with a transmission line and a switching circuit for selectively enabling one of the transmitters of one of the transceiver pairs and disabling the other and selectively utilizing one of the receivers of the other of the transceiver pairs and not the other to selectively reverse an egress side and an ingress side of the lane.

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Somerville, MA, United States of America

Michael C St Germain