Tela Innovations, Inc.

Texas Instruments Corporation

Other

Multibeam Corporation

Applied Materials, Inc.

Tel Innovations, Inc.

Michael C Smayling

Scott T Becker

David K Lam

Kevin M Monahan

Theodore A Prescop

Giovanni Santin

Giulio Giuseppe Marotta

Sebastiano D'Arrigo

Georges Falessi

Manuel L Torreno, Jr, Deceased

Satwinder S Malhi

Pietro Piersimoni

Iano D'Arrigo

Taylor R Efland

David A Baglee

Jonathan R Quandt

Daryl Fox

Stephen A Keller

Mousumi Bhat

Ronald N Parker

Cristina Lattaro

Michael P Duane

Luciano Talamonti

Klaus A Anselm

Misako A Matsuoka

Jack Reynolds

Satoru Fukawa

Ross Eliot Teggatz

Oh-Kyong Kwon

Carole Lambert

Jim Mali

Louis N Hutter

James Robert Todd

Giovanni Naso

Joseph A Devore

Dhrumil Gandhi

James L Paterson

Roy Clifton Jones, Iii

Wai Tung Ng

Douglas P Verret

Alec James Morton

Michael Duane

Giuliano Imondi

Frank K Tittel

Brian Reed

Sossio Vergara

Susie Xiuru Yang

William L Wilson, Jr

James A Tuvell

Roland Sauerbrey

Abnash C Sachdeva

George Falessi

Lembit Soobik

John Anthony Rodriguez

Donald J Redwine

Giulio-Giuseppe Marotta

Jihong Chen

Dennis J Yost

Joseph N Hong

Karl F Smayling

Giovani Santin

Mamoru Itoh

Alister C Young

Michael A McAweeney

Stephen Fairbanks

Manuel L Torreno, Jr Deceased

Manuel J Torreno, Jr Deceased

Shiany Oemardani

Manuel Torreno

James Reynolds

Methods, tools and systems for patterning of substrates using charged particle beams without photomasks, without a resist layer, using multiple different processes (different chemistry processes and/or different ones of material deposition, removal and/or modification) in the same vacuum space, wherein said processes are performed independently (without cross-interference) and simultaneously. As a result, the number of process steps can be reduced and some lithography steps can be eliminated, reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Also, because such processes are resist-less, layer-to-layer registration and other column control processes can be performed by imaging previous-layer features local to (or in contact with) features to be written in a next layer as designated by the design layout database.

Precision substrate material multi-processing using miniature-column charged particle beam arrays

Methods, systems and devices for using charged particle beams (CPBs) to write different die-specific, non-volatile, electronically readable data to different dies on a substrate. CPBs can fully write die-specific data within the chip interconnect structure during the device fabrication process, at high resolution and within a small area, allowing one or multiple usefully-sized values to be securely written to service device functions. CPBs can write die-specific data in areas readable or unreadable through a (or any) communications bus. Die-specific data can be used for, e.g.: encryption keys; communications addresses; manufacturing information (including die identification numbers); random number generator improvements; or single, nested, or compartmentalized security codes. Die-specific data and locations for writing die-specific data can be kept in encrypted form when not being written to the substrate to conditionally or permanently prevent any knowledge of said data and locations.

Secure permanent integrated circuit personalization

An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

Methods, structures, and designs for self-aligning local interconnects used in integrated circuits

Methods and systems for direct atomic layer etching and deposition on or in a substrate using charged particle beams. Electrostatically-deflected charged particle beam columns can be targeted in direct dependence on the design layout database to perform atomic layer etch and atomic layer deposition, expressing pattern with selected 3D-structure. Reducing the number of process steps in patterned atomic layer etch and deposition reduces manufacturing cycle time and increases yield by lowering the probability of defect introduction. Local gas and photon injectors and detectors are local to corresponding columns, and support superior, highly-configurable process execution and control.

Patterned atomic layer etching and deposition using miniature-column charged particle beam arrays

A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

Super-self-aligned contacts and method for making the same

An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.

Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid

Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid

Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. The first-metal structure layout shapes are positioned on a first-metal vertical grid having at least eight first-metal gridlines. At least six contact structures are formed from substantially rectangular shaped contact structure layout shapes in physical and electrical contact with corresponding ones of at least six of the gate structures. A total number of first-transistor-type-only gate structures equals a total number of second-transistor-type-only gate structures within the region. At least four transistors of a first transistor type and at least four transistors of a second transistor type collectively form part of a logic circuit within the region.

Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures

A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Integrated circuit cell library for multiple patterning

Growing community of inventors

Fremont, CA, United States of America

Michael C Smayling