Tektronix, Inc.

Other

Michael C Seckora

Benjamin A Ward

Ahmed M Said

Methods and apparatus provide for electrical coupling of electrical components to traces on a substrate such that impedance mismatches otherwise experienced in high frequency operation are avoided. Connecting elements having length, width, and thickness, are provided for terminals of a component to be connected to a trace. The connecting element is electrically coupled between the terminal and the trace, typically by soldering. The dimensions of the connecting element are chosen to reduce or eliminate the impedance mismatch which would result from a direct connection between the trace and component. Connecting elements are generally L-shaped, i.e., having first and second planar portions perpendicular with respect to each other, and having a curving portion that connects the first and second planar portions. In one embodiment, dimensions of at least a portion of the connecting element are such that its width increases as its distance from a ground plane within the substrate increases.

Impedance matching connection scheme for high frequency circuits

A repeatable finite anti infinite impulse response integrated circuit structure has a plurality of filter units programmably interconnected, with each filter unit having a pair of repeatable cells. Each cell has a coefficient stage for receiving a filter coefficient, a mixer stage for multiplying a selected one of a plurality of input signals by the filter coefficient, an accumulator stage for selectively delaying an input accumulation signal, and a summation stage for adding the input accumulation signal to the weighted signal to produce an output accumulation signal. With appropriate programming many desired finite/infinite impulse response filter configurations may be achieved.

Repeatable finite and infinite impulse response integrated circuit

A barrel shifter or multiply/divide integrated circuit (IC) structure includes a plurality of stages in series. The number of stages is a function of the number of bits in an input digital data word, and each stage in sequence provides for a different power of two rotary or multiply/divide shift of the digital data word at the input if selected. A multiplexer in each stage selects as an output either the shifted digital data word or the input digital data word for output to the next stage according to a shift amount select command. At the input and output of the series of stages an additional reversal multiplexer selects in response to a shift direction command either the digital data word or a reversed version of the digital data word, which determines the effective direction of the shift in the stages. Logic may be included in each stage to determine whether the shift operation is a rotary or multiply/divide shift operation.

Barrel shifter or multiply/divide IC structure

A finite impulse response (FIR) digital filter (100, 170, 175, 180) incorporates both symmetric and transposed structures in a configuration that suites ASIC implementation. The filter coefficients can be arranged in ascending order to implement coefficient block floating point, or in descending order. To further facilitate coefficient block floating point, filter coefficients are chosen so that each cell has an exponent value equal to or greater than that of a preceding cell. A right shift is provided between adjacent cells to equate the exponent value of a sum output of a preceding cell with that of the succeeding cell. Variable decimation is provided by downloading appropriate filter coefficient and adjusting a decimation forward clock. Multiple channels can also be accommodated.

Symmetric transposed FIR digital filter

A sequence of events detector provides a way to continuously monitor serial digital data and precisely define the behavior that it must exhibit in order to qualify as the sequence of events that the user wishes to detect. A plurality of evaluation windows each sequentially examine the behavior of one or more signals, comparing this behavior with predefined criteria. Each evaluation window is activated to begin its portion of the overall evaluation process by a match signal from the preceding window, indicating that its predefined criteria were met. In one version, a sequence starting circuit activates the first evaluation window in response to an external signal or the occurrence of a predefined condition, and a multiplexer trigger source circuit selects as the overall detector output the match signal output of the last evaluation window used to define the overall sequence of events. In another version, each evaluation window explicitly reports a failure if its predefined criteria are not met.

Sequence of events detector for serial digital data which selectively

A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into 'n' CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of 'n' elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

Analog-to-digital converter system

A serial-to-parallel analog CCD GaAs device provides high speed A/D or D/A conversion. A high speed analog signal is sampled by shifting the analog data serially into 'n' CCD elements. Then a parallel load pulse transfers the analog data into multiple CCD holding elements. A bank of A/D converters converts the analog data. Conversely, the outputs of a bank of D/A converters are loaded in parallel into a serial CCD device of the 'n' elements. The serial CCD device is shifted out serially to complete the conversion to an analog signal.

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Gervais, OR, United States of America

Michael C Seckora