Teradyne, Inc.

Michael C Panis

Bradford B Robbins

John Robert Pane

Richard Pye

Howard Lin

Jeffrey S Benagh

Steve Munroe

An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.

Identifying failures in device cores

An example test system includes instruments for controlling testing. Each instrument may be controlled by a processing unit. Each processing unit may be configured to operate on portions of a test program relevant to an instrument that the processing unit controls. A synchronization mechanism operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller.

Bus synchronization system that aggregates status

A method of jitter measurement is provided and includes sampling a device-under-test (DUT) output signal, having a repeating pattern, using an asynchronous clock over a desired period of time and mapping the samples onto a single period of the repeating pattern. Each period of the repeating pattern is sampled at least twice. A sampling frequency of the asynchronous clock is based on user inputs. Sampling the DUT signal comprises capturing logical state information representing each edge of a single period of the DUT signal at least once. The method further includes, separating the samples into subsets and mapping the sample subsets onto a single period of the repeating pattern wherein the samples within a particular subset are mapped to a set of times which are in the same order as in which the samples were obtained, processing the samples within each subset independently of samples in other subsets, and combining results of the processed subsets and processing the combined results of the subsets.

Jitter measurement algorithm using locally in-order strobes

A jitter frequency determining system is provided that includes a comparator, a clock source, a latching circuit, a memory device and a processor. The comparator is adapted to receive at least one output signal from a device under test and compare the output signal to an expected signal. The output signal has a repeating pattern. The clock source is adapted to produce a sampling clock based on user inputs. The clock source is further adapted to change the time between locally-in-order strobes to adjust the measurement bandwidth. The latching circuit is adapted to obtain samples of the output signal according to the sampling clock. The memory device is adapted to store the sampled data. The processor is adapted to analyze the stored data to determine jitter and to express jitter as a function of frequency.

Jitter frequency determining system

A method of determining frequency components of jitter in a waveform is provided. The method includes strobing a waveform having a repetitive pattern. Forming a locally-in-order strobing scheme of a representative one of the repetitive pattern including subsets of locally-in-order strobes. Locating transition regions in the subsets of locally-in-order strobes. Determining random jitter associated for each transition region and determining jitter as a function of frequency.

Determining frequency components of jitter

A method of determining frequency components of jitter in a waveform is provided. The method includes conducting a plurality of locally-in-order strobings of the waveform. Changing the acquisition time associated with each locally-in-order strobing. Measuring jitter associated with each locally-in-order strobing and determining jitter as a function of frequency based on the measured jitter associated with each change of acquisition time.

A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates. A time measurement circuit measures timing characteristics of the device under test, and a parametric measurement circuit measures steady-state characteristics of the device under test.

Enhanced loopback testing of serial devices

A pin electronics circuit for automatic test equipment includes first and second sampling circuits for sampling first and second legs of a differential signal produced by a DUT (Device Under Test). Timing signals activate the first and second sampling circuits to sample the legs of the differential signal at precisely defined instants of time to produce first and second collections of samples. To deskew the legs of a differential signal with respect to each other, corresponding features within the first and second collections are identified and a difference is taken between them. The differential skew can then be applied to correct measurements of differential signals.

Deskewed differential detector employing analog-to-digital converter

A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter. The time interval between successive rising edges of the output signals precisely match the time interval between successive rising edges of the input signals. Although the pre-conditioner preserves the edge locations of its input signals, the frequency of the signals it sends to the timer/counter is 1/N times the input frequency. The pre-conditioner thus enables to the timer/counter to measure closely spaced, consecutive edges of inputs over a low-bandwidth path. Multiplexors, inverters, and additional frequency dividers may be included with the pre-conditioner to enhance its functionality.

Pre-conditioner for measuring high-speed time intervals over a low-bandwidth path

A method for operating automatic test equipment for capturing digital data produced by a semiconductor device under test, whereby the digital data is repetitively sampled to produce a series of sampled data pairs. The digital data and the sampling frequency can be non-coherent. As a result, the digital data can be sampled early relative to some bits and late relative to other bits. The sampled data pairs that are captured while these shifts take place, from early-to-late sampling or from late-to-early sampling, are then assigned to respective groups. A minimum number of bit patterns, corresponding to the sampled digital data, is then derived from contiguous groups of sampled data pairs, and compared with expected bit patterns. The method is especially useful for capturing digital data with drifting frequency.

Method for capturing digital data in an automatic test system

A tester that produces digital timing signals having fast data rates including multiple groups of timing generators, multiple 'exclusive-or' gates, and an 'or' gate. Each group of timing generators is connected to an exclusive-or gate, and the output of each exclusive-or gate is coupled to the or gate. The digital timing signals are encoded such that the timing generators in each group may assert timing pulses only during specified cycles within a series of clock cycles. Each combination of timing generators within a group either asserting their respective encoded timing signals, or not asserting any timing signals during the series of clock cycles, generates a unique serial data stream. The serial data streams generated by the groups of timing generators are then combined to produce a new digital timing signal having a data rate that is faster than the data rate of the encoded digital timing signals.

High speed serial data pin for automatic test equipment

A method for automatically testing digital electronic circuits and performing time measurements whereby a digital signal having a frequency f1 is sampled at a rate equal to f2. The sampling frequency f2 is either slightly less than or slightly greater than f1. As a result, the digital signal is sampled at either a slightly later position in time or a slightly earlier position in time during each successive period of the digital signal. After the entire interval of interest on the digital signal has been sampled, either the number of logical high data samples or the number of logical low data samples is determined. Finally, the number of data samples is multiplied by the effective time period between data samples. In this way, pulse widths on digital signals can be measured with both high resolution and good linearity. This method of time measurement may also be used to calibrate an electronic circuit tester.

Growing community of inventors

Somerville, MA, United States of America

Michael C Panis