Intelect Communications, Inc.

Intelect Systems Corporation

Terraforce Technologies Corp.

Michael C Greim

James R Bartlett

A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. A dual port SRAM (DPSRAM)( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for transfer of the block of data from the global resources to the designated CPU ( ).

DSP with distributed RAM structure

A multi-processor system includes a global bus ( ) with a global address space and a plurality of processor nodes ( ). Each of the processor nodes ( ) has a CPU ( ) interfaced with a local bus having a local address space. A dual port SRAM (DPSRAM) ( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for data transfer. Each of the CPU's ( ) can communicate directly with another of the CPU's ( ) through an interprocessor communication network. This network includes a Bi-FIFO ( ). The CPU ( ) is operable to interface with a predefined type of memory having a defined memory access protocol different from that of the Bi-FIFO ( ). Therefore, a translator circuit is required to convert memory access commands and data flow to a compatible format with that of Bi-FIFO ( ). This includes a programmable bi-directional pipeline circuit ( ) and also a predecode circuit ( ) to allow selection of one of a plurality of Bi-FIFOs to allow the CPU ( ) to communicate with different Bi-FIFOs within the same memory space.

DSP intercommunication network

A multi-processor system includes a global bus ( ) having associated therewith a global address space with a plurality of processor nodes ( ) associated therewith. Each of the processor nodes ( ) has a CPU ( ) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. The global bus ( ) has associated therewith an arbiter ( ). Each of the processing nodes interfaces with a global register ( ) which is operable to contain paging registers for each of the files. A portion of the memory space in the processing nodes is paged over to the global address space. To facilitate the upper address bits of the global address space they are stored in a paging register and then the arbiter ( ) selects these upper address bits for output to the bus. The lower address bits are provided by the particular processor node that is accessing the global address space.

Paging method for DSP

A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18) is provided for interfacing between the global bus (14) and a system bus (12). Interrupts that are generated on the system bus (12) are mapped to the CPUs (20) through an interrupt controller (82). The interrupt controller (82) is operable to receive multiple interrupts and store these interrupts and their associated interrupt vectors. After storage, a gating register associated with each CPU (20) is examined to determine which interrupts are serviced by a particular CPU (20). If an interrupt is received that is to be serviced by one or more of the CPUs (20), then an external interrupt is generated for that CPU (20). Once the external interrupt is generated, the CPU will then examine a flag register associated therewith, which flag bits are set only if the interrupt controller (82) has determined that the CPU (20) is to receive the interrupt in accordance with the contents of the gating registers. The CPU (20) will then service the particular interrupts directed thereto by accessing the stored interrupt vectors. Once all CPUs (20) that are to service an interrupt have retrieved the interrupt vector, an acknowledgment signal is sent back to the system bus (12).

Growing community of inventors

Garland, TX, United States of America

Michael C Greim