Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Michael C Day

Christian Laszlo Belady

Eric C Peterson

Shaun Lee Harris

Stuart C Haden

Lisa Heid Pallotti

Richard A Schumacher

Brian Matthew Johnson

John A Nerl

June E Goodwin

Vicki L Smith

Terrel L Morris

Brent A Boudreaux

Gary Williams

Roy M Zeighami

Paul Anthony Wirtzberger

Rajakrishnan Radjassamy

Jeffrey Christenson

Jeffrey N Metcalf

Paul T Artman

James Steven Wells

David A Klein

Greg Huff

Ronald J Bellomlo

A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

Memory module with a predetermined arrangement of pins

An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Multi-processor module

One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.

Double-high DIMM with dual registers and related methods

A circuit comprising multiple circuit boards is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Processor and power supply circuit

A high performance processor assembly is electrically connected to a power supply so as to minimize voltage variations associated with the supply of power to the processor assembly. The processor assembly is fabricated on a multilayered printed circuit board. Power is supplied to components on the printed circuit board by way of parallel and split power planes. The parallel and split power planes reduce inductance and increase capacitance associated therewith. The reduced inductance reduces voltage variations caused by load transient currents. Capacitors are electrically connected to the power planes by way of multiple vias to further reduce inductance.

The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.

Packaging architecture for 32 processor server

Growing community of inventors

Allen, TX, United States of America

Michael C Day