International Business Machines Corporation

Lockheed Martin Corporation

Michael C Dapp

James Warren Dieffenderfer

Vincent John Smoral

Richard Edward Nier

David B Rolfe

Thomas Norman Barker

Billy J Knowles

Clive Allan Collins

Donald Michael Lesmeister

Eric Eugene Retter

Robert Reist Richardson

Richard Ernest Miles

James Robert Stupp

Peter Michael Kogge

Paul Amba Wilkinson

Nicholas Jerome Schoonover

David Christopher Kuchinski

Donald George Grice

Donald G Grice

Jeremy Impson

Kenneth B Donovan

John Moody

Eric C Lett

Robert J Szczerba

Adam L Jung

Joel J Tleon

Sai Lun Ng

Paul W Thurm

David Christoper Kuchinski

One embodiment is directed to providing access between external systems and embedded vehicle electronic systems. That is, an interface module may receive information from a system external to the vehicle, determine an embedded system of the vehicle to which to provide the information, and provide the information to the embedded system. Similarly, the interface module may receive information a embedded electronic systems of a vehicle, determine a system external the vehicle to which to provide the information, and provide the information to the external system.

Methods and apparatus for providing access to vehicle electronic systems

A system ensures safety and security of teams of collaborative autonomous unmanned vehicles in executing a mission plan. The system includes a plurality of components, a first device, a second device, and a third device. The plurality of components perform situation analysis, mission planning, mission replanning, mission plan execution, and collaboration between the autonomous unmanned vehicles. The first device identifies safety critical components of the plurality of components. The second device identifies security sensitive components of the plurality of components. The third device isolates the safety critical components from contamination by other components of the plurality of components. The third device isolates security sensitive data from contaminating non-security sensitive components of the plurality of components.

System for controlling unmanned vehicles

A high level of security and fault tolerance is provided in a digital network by use of highly secure infrastructure of user transparent signalling for communicating detection of signals at a network node having characteristics of a potential attack to another node and controlling communications at routers at the node from another node in response to the user transparent signals. A processor is connected to the routers and the network through an encryption engine and includes a manager object to issue control commands to nodes of a locally lower hierarchy tier and managed objects to detect potential attacks and exercise control over the routers responsive to signals from a node of a locally higher hierarchy tier. Identifications are provided for communications between nodes regardless of whether or not a corresponding user is identified and communications are logged. Thus any network session comprises one or more secure sessions in a plurality of security domains and any fault or potential attack can be compartmentalized to a node or sector of the network and isolated while normal communications are continued over redundant network links.

Active intrusion resistant environment of layered object and compartment keys (airelock)

Security policy manager devices are leveraged by manager objects to use highly secure user transparent communications to provide detection of questionable activities at every node, automatic collection of information related to any potential attack, isolation of the offending object with arbitrary flexibility of response (e.g. flexibly determining the level of certainty of an attack for initiation of a response in accordance with the number of nodes to be partitioned that is determined by the collected data concerning the potential attack), changing trust relationships between security domains, limiting the attack and launching offensive information warfare capabilities (e.g. outbound from the compromised node while limiting or eliminating inbound communications) in log time and simultaneously and/or concurrently in different but possibly overlapping sections or segments of a digital network of arbitrary configuration.

Real time active network compartmentalization

Signatures of character strings in a document which may indicate a possible intrusion into or attack on a networked computer system or node thereof or other security breach are detected at high speed using a hardware accelerator within the environment of a hardware parser accelerator. An interrupt or exception can thus be issued to a host CPU before a command which may constitute such a security breach, intrusion or attack can be made executable by parsing of a document. The CPU can initiate network control measures to prevent or limit the intrusion.

Intrusion detection accelerator

A hardware accelerated validation parser is provided to remove a large portion if not all of the processing and overhead burden of validation parsing from a host processor by parallel access to both a state table and a data dictionary based on a token and merging and selective redirection of the respective outputs thereof; a portion of a transition control word (TCW) formed by the merged data being used to advance through the state table and a portion of the TCW being used to control formation of a tree structured data object (TSDO) corresponding to a text document in a language such as XML&#x2122; which supports interoperability and platform independence. A stack is provided to accommodate nesting of elements and aggregate elements. The formation of the TSDO can be and preferably is performed asynchronously and autonomously in parallel with the validation parsing.

Hardware accelerated validating parser

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. A fully distributed programmable router is provided by the processing memory elements that form a node. There is program compatibility for the fully scalable system.

APAP I/O programmable router

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

Fully distributed processing memory element

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Advanced parallel array processor (APAP)

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a 'cluster ring'. Corresponding nodes of eight cluster rings are connected into rings in the W dimension.

N-dimensional modified hypercube

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32 K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

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Endwell, NY, United States of America

Michael C Dapp