Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global

Michael C Coln

Gary Carreau

Robert W Adams

Yoshinori Kusuda

Tom W Kwan

Alain Valentin Guery

Lalinda D Fernando

Lejun Hu

Javier Alejandro Salcedo

Colin Gerard Lyden

Bernard Patrick Stenson

Srivatsan Parthasarathy

William Allan Lane

Stephen O'Brien

Matthew Thomas Canty

Christina B McLoughlin

Christophe Antoine

Mark Daniel De Leon Alea

Daniel Joseph Lucey

Cathal Murphy

Shrenik Deliwala

Christopher Peter Hurrell

Eric G Nestler

John M Wynne

Roderick McLachlan

John Jude O'Donnell

Shane Patrick Geary

Robert John Brewer

Bruce E Amazeen

Baozhen Chen

Avinash Gutta

John A McNeill

Mark D Maddox

Maitrey Kamble

Vinayak Mukund Kulkarni

Shane Geary

Paraic Brannick

Himanshu Jain

Sinead Maire McDermott

Mark De Leon Alea

Sinead Maire Mcdermott

Alan Bannon

Embodiments of the disclosure provide various nanogap sensor designs (e.g., horizontal nanogap sensors, vertical nanogap sensors, arrays of multiple nanogap sensors, various arrangements for making electrical connections to the electrodes of nanogap sensors, etc.), as well as various methods which may be used to fabricate at least some of the proposed sensors. The nanogap sensors proposed herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap.

Designs and fabrication of nanogap sensors

Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.

Methods and systems for readout of nanogap sensors

When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

Calibration techniques for SAR ADCs with on-chip reservoir capacitors

A signal gate is provided where the gate can be low impedance to allow a signal to pass or be high impedance to block it. The signal gate has two output nodes arranged such that during the blocking mode spurious signals passing through the gate by way of parasitic components are presented as common mode signals at the output nodes.

Signal gate, a sampling network and an analog to digital converter comprising such a sampling network

A method and a digital-to-analog converter (DAC) circuit involve forming an analog signal using charge sharing operations. The DAC circuit includes a plurality of digital components with associated parasitic capacitances. The digital components are activated based on a digital input code, such that charge is shared among the parasitic capacitances to form a first analog signal proportional to the digital input code. The digital components can also be activated based on a complementary code to form a second analog signal. The first analog signal and the second analog signal can be used to form, as a final output of the DAC circuit, an analog signal that is linearly proportional to the digital input code.

Digital-to-analog converter with digital charge sharing components

Apparatus and methods calibrate one or more gain ranges for errors. A system can identify offset error and amplification error that occurs when the system transitions from amplifying an input signal by a first gain factor to amplifying the input signal by a second gain factor. To identify the amplification error, the system can compare the slope of the data signal in a source or reference gain range with the slope of the data signal in the destination gain range. To identify the offset error, the system can compare the amplitude of the data signal in a destination gain range with an expected value in the destination gain range.

Gain calibration

An accurate, cost-efficient temperature sensor may be integrated into an integrated circuit (IC) using common materials as the IC's interconnect metallization. The temperature sensor may include an impedance element having a length of metal made of the interconnect metal, a current source connected between a first set of contacts at opposite ends of the impedance element, and an analog-to-digital converter connected between a second set of contacts at opposite ends of the impedance element. The temperature sensor may exploits the proportional relationship between the metal's resistance and temperature to measure ambient temperature. Alternatively, such a temperature sensor may be used on disposable chemical sensors where the impedance element is made of a common metal as conductors that connect a sensor reactant to sensor contacts. In either case, because the impedance element is formed of a common metal as other interconnect, it is expected to incur low manufacturing costs.

On-chip temperature sensor using interconnect metal

Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels.

Apparatus and methods for reducing common-mode noise in an imaging system

The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal.

Split-path data acquisition signal chain

Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.

Guarded electrical overstress protection circuit

A detector circuit can include an integrator having an amplifier, a first feedback capacitor connected between an input and output of the amplifier, one or more additional feedback capacitors connected by at least one switch between the input and output of the amplifier, and a shunt capacitor connected to the output of the amplifier. The shunt capacitor can be selected to have a capacitance value greater than that of a minimum but less than that of a maximum feedback capacitance. The detector circuit can further include a sampling circuit having a sampling capacitor connected to the output of the integrator amplifier through at least one switch, wherein the sampling capacitor is separate from the shunt capacitor. A computed tomography imaging apparatus can include the detector circuit.

Reduced-noise integrator, detector and CT circuits

A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.

Correlated double-sample differencing within an ADC

A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

Electrical overstress protection using through-silicon-via (TSV)

The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.

Programmable linearity correction circuit for digital-to-analog converter

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Lexington, MA, United States of America

Michael C Coln