Freescale Semiconductor,inc.

Michael C Butner

Ronghua Zhu

Vishnu Khemka

Amitava Bose

Vijay Parthasarathy

Bernhard Grote

Todd C Roggenbauer

Tahir Arif Khan

Paul Hui

Shifeng Shen

Higher voltage device isolation structures (') are provided for semiconductor integrated circuits having strongly doped buried layers (&#x2033;). One or more dielectric lined deep isolation trenches (&#x2032;&#x2033;) separates adjacent device regions (). Electrical breakdown (BVdss) between the device regions () and the oppositely doped substrate (&#x2033;) is found to occur preferentially where the buried layer (&#x2033;) intersects the dielectric sidewalls (&#x2033;) of the trench (&#x2032;&#x2033;). The breakdown voltage (BVdss) is increased by providing a more lightly doped region () of the same conductivity type as the buried layer (&#x2033;), underlying the buried layer (&#x2033;) at the trench sidewalls (&#x2033;). The more lightly doped region's () dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (&#x2033;) and it extends substantially entirely beneath the buried layer (&#x2033;) or to a distance () extending about 0.5 to 2.0 micro-meters from the trench sidewall (&#x2033;). In a preferred embodiment, the trench (&#x2032;) is split into two portions (&#x2032;) with the semiconductor therein () ohmically coupled to the substrate ().

Robust deep trench isolation

A method of manufacturing a semiconductor component includes forming a first electrically insulating layer () and a second electrically insulating layer () over a semiconductor substrate (). The method further includes etching a first trench () and a second trench () through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench () through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion () and a second portion () interior to the first portion. The method still further includes forming a third electrically insulating layer () filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer () in the second portion of the third trench.

Method of manufacturing a semiconductor component

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Phoenix, AZ, United States of America

Michael C Butner