Motorola Corporation

International Business Machines Corporation

Data General Corporation

Freescale Semiconductor,inc.

Michael C Alexander

James Allan Kahle

Aubrey Deene Ogden

Gianfranco Gerosa

Arturo L Arizpe

Belliappa Manavattira Kuttanna

Kathryn C Stacer

Glenn E Hunt

Arthur R Piejko

David F Greenberg

Carmine Nicoletta

Gerald L Lozano

Gerald O Manktelow

Each cacheline of a unified cache storing information is marked as incoherent if the information was acquired incoherently or marked as coherent if the information was acquired coherently. A subsequent incoherent read access to a cacheline can result in a cache hit and a return of the cached information regardless of whether the cacheline is marked as coherent or incoherent. However, a subsequent coherent read access to a cacheline marked as incoherent will be returned as a cache miss regardless of whether the cacheline includes information sought by the coherent read access. In response to a cache miss for a coherent read access, a global snoop is initiated so as to query all other target components within the same coherency domain. In contrast, a cache miss resulting from an incoherent read access is processed using a non-global snoop to a limited set of one or a few target components in the coherency domain.

Processing of coherent and incoherent accesses at a uniform cache

A data processor (10) incorporates instruction regulating or 'throttling' circuitry (31) for limiting consumed power. A user visible register maintains an INTERVAL field by which instruction fetch from an instruction cache (14) is periodically delayed. This INTERVAL field may be adjusted to suit the power budget of the data processor.

Data processor with circuit for regulating instruction throughput while

A system for data synchronization in a bus interface unit (12) controls the flow of data between data processor (10) operating at a higher clock rate and the address and data buses operating at a lower clock rate. The data synchronization system incorporates circuit paths operating in four different clock domains: core-rate, bus-rate, transfer-rate, and receive-rate. Circuits processing data solely at the higher clock rate of the data processor or the lower clock rate of the address and data buses operate in the core-rate or bus-rate domains, respectively. The transfer-rate domain is used to transfer data from the core-rate to the bus-rate. Conversely, the receive-rate domain is used to transfer data from the bus-rate to the core-rate. The data synchronization system provides a general solution to the problem unreliable half cycle data paths.

System for data synchronization between two devices using four time

A method and apparatus for synchronizing multiple busses having different cycle times in a data processing system (10). The present invention synchronizes multiple clocks having different phase and frequencies without redundant use of phase lock loop units. An initial unit (7) receives an external system clock having an initial phase and frequency. An internal clock (112) is generated which is a phase and frequency adjusted derivation of the system clock. From this internal clock (112) a global clock (101) for use within the data processor (10) is generated. A second unit (9) receives the internal clock (112) and performs phase adjustment to provide a peripheral clock (114). The provision of the internal clock (112) detaches the dependency of peripheral clock (114) generation from the global clock (101), while maintaining a phase relationship with the global clock (101). In one embodiment, the present invention is implemented without the costly use of multiple phase lock loops.

Method and apparatus for synchronizing multiple clocks

A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.

Circuitry and method for reducing power consumption within an electronic

A raster scan CRT character generator comprising a memory having dot patterns for a plurality alphanumeric characters stored therein and a multiplexer, controlled by a signal from the memory, for selecting one of a plurality of sets of inputs to be used for determining the state of dots in the character field other than the character dot pattern.

Video terminal character generator

Apparatus and method for simultaneous display of alphanumeric characters of variable character density on a raster scan CRT monitor is disclosed. Circuitry is provided to supply multiple sources of timing for terminal operations, to switch among timing sources without display degradation, and to vary the number of dots per raster line that constitute a character field. The density of displayed characters may be changed, under user control, for each character row.

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Austin, TX, United States of America

Michael C Alexander