Analog Devices,inc.

Analog Devices International Unlimited Company

E.i. Technology Limited

E.i. Technology Unlimited Company

Michael Byrne

Adrian Sherry

Colin Charles Price

Derek J Hummerston

Nicola M O'Byrne

Colin Gerard Lyden

Damien Joseph McCartney

Claire Croke

Aine McCarthy

John M Wynne

Stephen Daniels

Mary McCarthy

Giovanni C Dotta

Fiona Treacy

Dan O'Donovan

Sean Wilson

John R Reidy

Michael G Curtin

Keith Fawcett

Michael Guinee

Fergus Flynn

Simon Smith

James Duignan

Colin Price

Ronan Doyle

Rona Doyle

Daniel O'Shea

David Keating

Niall Mccollum

Brendan Barry

Aine Mccarthy

David Hannick

Shane Linnane

Daniel O'SHEA

Various examples are directed to methods and system of managing a sensor. A measurement system may receive from the host device, a first register map describing a first configuration of the measurement system for the first sensor. The first configuration may indicate a first measurement frequency for the first sensor. The measurement system may configure a switch matrix to provide a first excitation signal to the first sensor. The measurement system may configure the switch matrix to connect an analog-to-digital converter (ADC) of the measurement system to the first sensor. The measurement system may sample a first raw sensor signal from the first sensor with the ADC at a first measurement frequency described by the first configuration. The measurement system may generate first digital measurement data based at least in part on the first raw sensor signal and send the first digital measurement data to the host device.

Measurement system

Various examples are directed to systems and methods for managing a sensor. A measurement system may receive, from a host device, a first register map describing a first configuration of a measurement system. The first configuration may be associated with a first sensor. The measurement system may compare the first register map to an error rule set indicating inconsistent register map arrangements. After comparing the first register map to the error rule set, the measurement system may configure a switch matrix of the measurement system to sample the first sensor according to the first configuration of the measurement system. The measurement system may receive a plurality of samples from a first sensor and generate first digital measurement data based at least in part on the plurality of samples.

A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

Method for placing a device in a selected mode of operation

A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements which sequentially pass a '1' along the chain in response to a clock signal. Each element is also responsive to a respective select signal and, if selected, behaves like a latch, whereas if unselected it behaves as if it were not there.

Programmable converter having an automatic channel sequencing mode

A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

System and method to place a device in power down modes/states and restore back to first mode/state within user-controlled time window

A smoke alarm device has an ASIC ( ) with an integrated photo detector ( ) and control circuit. The photo detector output is compared every ten seconds with an alarm threshold level in a comparator circuit ( ), with a sensitivity-decrease threshold in a comparator circuit ( ), and with a sensitivity-increase threshold in a comparator circuit ( ). A logic block ( ) causes sensitivity to be increased or decreased in which decreases take place at intervals of six hours and increases take place after 40 secs. The logic block ( ) provides for least sensitivity at power-up with rapid increases to the appropriate level according to the level of back-scatter caused by dust contamination. The logic block ( ) maintains a high signal on an interconnect terminal ( ) for four seconds after a test button ( ) is pressed so that a maintenance person can hear remote interconnected devices after the local device has stopped sounding. The logic block ( ) also stores a memory flag when is goes into alarm mode and modulates the horn at a different frequency at the next testing to indicate that it has historically sensed smoke since last tested.

Smoke alarm device

A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Digital filtering system

An IC chip having an analog-to-digital converter together with control circuitry for effecting switchover between normal-power mode and low-power mode. The control circuitry includes a first D-type flip-flop with reset which receives on its 'D' input a continuous high signal; on its differential clock inputs the flip-flop receives complementary logic signals derived from the 'conversion start' (CONVST) signal applied to one pin of an 8-pin chip. In normal mode, the CONVST signal is a short pulse having an initial negative-going (falling) leading edge, and the flip-flop responds to that leading edge by producing a high Q output (CONVEN). This signals the A/D converter to carry out a conversion. In low-power mode, the CONVST short pulse is positive. The subsequent negative-going (falling) trailing edge of the pulse activates the flip-flop to cause its Q output to go high and turn on the A/D converter. The control circuitry includes a second D-type flip-flop (this one with set) which receives on its D input the CONVST signal. The Q output. of the second flip-flop generates a mode switchover control signal (designated SLEEPB). During low-power mode, established by the use of positive-going CONVST pulses, the low CONVEN signal at the end of conversion clocks the second flip-flop to sample CONVST on its D input, thereby causing the Q output of the second flip-flop (SLEEPB) to go low and switch the A/D converter into low-power status.

Analog-to-digital converter with optional low-power mode

A D/A converter of the type provided with an amplifier to produce the analog output signal and formed as an IC chip. The chip includes a power voltage monitor to sense when the applied DC voltage is above a preset lower level and below a preset upper level. When that condition is sensed, the monitor activates a control circuit which in turn opens a transmission gate between the amplifier output circuit and the converter output terminal, and closes a transmission gate between the output terminal and ground. When the DC voltage goes above the preset upper level, and a valid digital word is loaded into the converter register and presented for conversion, the condition of the transmission gates is reversed to provide for normal operation of the converter.

D/A converter with means to prevent output signal instability

A converter for producing the function V.sub.out =V.sub.bias =V.sub.swing (1-2D), in which a DAC is combined with an operational amplifier and (typically) three or four resistors. A function of the voltage V.sub.swing, or a current corresponding thereto, is applied to the reference voltage input terminal of the DAC. The variable D is the DAC's digital input code, expressed as a decimal or fraction in the range between 0 and 1. The DAC output provides a suitably scaled and signed signal which is added to or subtracted from the offset signal V.sub.bias to produce V.sub.out.

Single-supply digital-to-analog converter for control function generation

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Limerick, Ireland

Michael Byrne