Groq, Inc.

Cray Incorporated

Michael Bye

Jonathan Alexander Ross

Dennis Charles Abts

Andrew Ling

Rahul Shah

Garrin Kimmell

Matthew Boyd

John Thompson

Albert Cheng

When reading and writing DRAM (dynamic random-access memory), the latency and bandwidth is often unpredictable with large variations. One reason is because all the DRAM memory banks require periodic refreshes and maintenance cycles that interrupt these accesses. DRAM refresh and maintenance cycles are synchronized with the read/write accesses in a mutually exclusive manner, hence, preventing the accesses from being interfered with by a refresh or maintenance cycle resulting in predictable latency and bandwidth performance during read/write operations.

Method to manage periodic dram refresh and maintenance scheduling for predictable dram data access

A system contains a network of processors arranged in a plurality of nodes. Each node comprises a respective plurality of processors connected via local links, and different nodes are connected via global links. The processors of the network communicate with each other to establish a global counter for the network, enabling deterministic communication between the processors of the network. A compiler is configured to explicitly schedule communication traffic across the global and local links of the network of processors based upon the deterministic links between the processors, which enable software-scheduled networking with explicit send or receive instructions executed by functional units of the processors at specific times, to establish a specific ordering of operations performed by the network of processors. In some embodiments, the processors of the network of processors are tensor streaming processors (TSPs).

Software-defined tensor streaming multiprocessor for large-scale machine learning

Embodiments include a system and method for generating RTL description of an electronic device provided for a design test and a test bench environment to drive stimulus into the electronic device, identifying at least one register to be verified during the design test, authoring a property list including a plurality of properties, wherein each property includes a cause and an effect, creating a new property instance upon receiving an enqueue cause, transitioning a property instance from a waiting state to a pending state based on a dequeue cause, advancing property instances from the pending state to an active state and then to an expired state based on a defined time window, creating a current solution space including a plurality of solutions, wherein each of the plurality of solutions includes a list of unused active effects, inserting property instances into each of the plurality of solutions when the property instance enters to active state, pruning solutions from the current solutions space which have not used a property instance entering the expired state, and computing a new solution space based on the current solution space and target transition.

System and method for verifying race-driven registers

Growing community of inventors

Chippewa Falls, WI, United States of America

Michael Bye