Golden Gate Technology, Inc.

Gg Technology, Inc.

Michael Burstein

Boris Ginzburg

Andrew Nikishin

Georgy Sergeev

Vladimir Zakladny

Mikhail Komorov

Alexander Kouznetsov

Methods and software for determining one or more boundary conditions for nets in a signal path are disclosed. The method generally includes determining an expected characteristic for at least one net in the signal path and determining a boundary characteristic for that net. Determining a boundary characteristic for the net may include multiplying the expected characteristic by a scaling factor to produce a scaled characteristic for the net, performing timing analysis of the signal path in accordance with the scaled characteristic (e.g., by calculating timing while assuming that the net has the scaled characteristic), determining if the signal path violates a timing constraint when the net has the scaled characteristic, and repeating the determination with a new scaled characteristic if timing is violated. Advantageously, maximum and/or minimum values may be determined for characteristics of signal path nets that still satisfy timing constraints.

Methods and software for determining net bounds for placing and routing

Methods and software for methods and software for placing and routing a signal path in an integrated circuit layout are disclosed. The signal path generally includes a plurality of cells and combinational paths having at least one net between said cells. The method includes determining whether an adjacent cell can be swapped with a selected cell (e.g., where the selected cell is one of the cells of the signal path and the adjacent cell is adjacent to the selected cell in the layout), determining whether a delay of the signal path decreases after swapping positions of the adjacent cell and the selected cell, and determining whether swapping the adjacent and selected cells causes a timing violation in another signal path of the layout. The present invention advantageously provides an automated method of improving the timing characteristics of poorly performing signal paths, without causing timing violations in other signal paths in the same integrated circuit.

Methods of automatically placing and routing for timing improvement

Methods and software for placing or re-placing integrated circuit cells and routing or re-routing nets between the cells in an integrated circuit layout. The method includes selecting a region of the cells in the integrated circuit layout, selecting a cell within the selected region, locating a border point where a net coupled to the selected cell crosses a border of the selected region, and moving the selected cell within the selected region to improve a timing characteristic (e.g., a wire length, capacitance, or other characteristic of the net that affects timing or delay) of the net. The method and software advantageously improve the placement of cells and routing of wires around congested or reserved regions after global routing has been performed, without causing timing violations in other signal paths on the integrated circuit device, in a computationally efficient manner.

Methods and software for placement improvement based on global routing

A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.

Method for matching timing on high fanout signal paths using routing guides

A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and/or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.

Method of placing and routing for power optimization and timing closure

A method, algorithm, software, architecture and/or system for placing circuit blocks and/or routing wires in a circuit design is disclosed. In one embodiment, a method of placing can include: (i) determining a first signal path between first and second circuit blocks and determining a second signal path between first and third circuit blocks; and (iii) placing the first circuit block relative to the second and third circuit blocks in a position related to a switching activity of the first and second signal paths. The circuit blocks can include standard cells configured to implement a logic function, other components, or integrated circuits, for example. The switching activity can include a switching frequency determination based on simulation results of the first and second signal paths between the circuit blocks. Embodiments of the present invention can advantageously reduce power consumption as well as supply noise by optimally placing circuit blocks in an automated place-and-route flow. Further, signal integrity problems due to non-optimal circuit block or component placement can be minimized.

Method for circuit block placement and circuit block arrangement based on switching activity

A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a switching activity for signal path between a first circuit block and a second circuit block; and (ii) routing the signal path substantially in a connectivity layer related to the switching activity of the signal path. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The switching activity can include a switching frequency determination based on simulation results of the signal path between the circuit blocks. Embodiments of the present invention can advantageously reduce power consumption as well as supply noise by optimally routing signal paths between circuit blocks in an automated place-and-route flow. Further, signal integrity problems due to non-optimal routing can be reduced or minimized relative to conventional techniques.

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Cupertino, CA, United States of America

Michael Burstein