Intel Corporation

Apple Inc.

Intel Mobile Communications Gmbh

Michael Bruennert

Andreas Menkhoff

Thomas Bauernfeind

Zdravko Boos

Georgios Yorgos Palaskas

Markus Schimper

Paolo Madoglio

Bernd-Ulrich Klepser

Andreas Boehme

An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

Apparatuses and methods for shifting a digital signal by a shift time to provide a shifted signal

This document discusses apparatus and methods for reducing energy consumption of digital-to-time converter (DTC) based transmitters. In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive phase information from a baseband processor and to provide a first modulation signal for generating a wireless signal, and a detector configured to detect an operating condition of the wireless device and to adjust a parameter of the DTC in response to a change in the operating condition.

Power saving technique for digital to time converters

A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.

Circuit, a method and a synthesizer for generating a synthesized signal with a selectable frequency

A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.

System and method for generating a data dependent clock for a DAC in a modulator

A digital-to-analog converter for converting digital values to an analog output signal includes a first converter section and a second converter section operating at different conversion rates. A first analog signal provided by the first converter section and a second analog signal provided by the second converter section are combined to obtain the analog output signal. The concept may be used in fields of DAC applications where the sample rate is much higher than the signal bandwidth. The limited signal bandwidth means that the maximum change between two neighboring samples is a small fraction of the whole DAC range. The first converter section may cover a large range of values, whereas for the second converter section a relatively small range of values may be sufficient.

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Unterhaching, Germany

Michael Bruennert