Cisco Technology, Inc.

Pensando Systems Inc.

Silicon Graphics, Incorporated

Cray Research, Inc.

Other

Advanced Micro Devices Corporation

Nuova Systems, Inc.

Michael Brian Galles

Shrijeet Mukherjee

Hemant Vinchure

Luca Cafiero

Randal Steven Passint

Greg Thorson

Silvano Gai

Krishna Doddapaneni

Scott David Johnson

Jonathan S Turner

William Norman Eatherton

Sarat Kamisetty

Martin M Deneroff

Daniel E Lenoski

Mario Mazzola

J Bradley Smith

Robert E Newhall

David Scott Feldman

David Delano Ward

Pradeep Kumar Kathail

Steven C Miller

Rami Zemach

Diego Crupnicoff

Elango Ganesan

Michael Freed

Zubin D Dittia

Vipin Jain

John H W Bettink

Jeffrey Scott Kuskin

Subbarao Arumilli

Vitaly Sukonik

Stephen Paul Belair

Michael Laor

Lawrence Rolfe Kreeger

John Andrew Fingerhut

Balakrishnan Raman

Alessandro Fulli

Moshe Voloshin

Murty Subba Rama Chandra Kotha

Harinadh Nagulapalli

Vishwas Danivas

Sameer Kittur Subrahmanya

Sanjay Shanbhogue

David M Parry

Neel C Patel

Kit Chiu Chu

Cesare Cantu

Anant Deepak

Francis Matus

David Antony Clear

Weihuang Wang

Jon C Gibbons

Ronald E Nikel

Alexandru Seibulescu

Mahesh Machineni

Kecheng Qian

John H Bettink

Hemant M Vinchure

Embodiments herein describe selectively bypassing a networking pipeline in a DPU. For example, instead of a packet being processed by both the networking pipeline and a DMA pipeline in the DPU, the packet is only processed by the DMA pipeline. This can reduce latency for packets that do not have network-heavy tasks associated with them, such Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE) packets. In addition, the DPU can perform load balancing between different instances of the pipelines in the DPU.

Programmable traffic ingress direction for reduced latency in a DPU

Described are platforms, systems, and methods for resource fairness enforcement. In one aspect, a programmable input output (IO) device comprises a memory unit, the memory unit having instructions stored thereon which, when executed by the programmable IO device, cause the programmable IO device to perform operations comprising: receiving an input from a logical interface (LIF); determining, by at least one meter, a metric regarding at least one resource used during a processing of the input through a programmable pipeline; and regulating additional input received from the LIF based on the metric and a threshold for the at least one resource.

Resource fairness enforcement in shared IO interfaces

PCIe devices installed in host computers communicating with service nodes can provide virtualized NVMe over fabric services. A workload on the host computer can submit an SQE on a NVMe SQ. The PCI device can read the SQE to obtain a command identifier, an OpCode, and a namespace identifier (NSID). The SQE can be used to produce a LTP packet that includes the opcode, the NSID, and a request identifier. The LTP packet can be sent to the service node, which may access a SAN in accordance with the opcode and NSID, and can respond to the LTP with a second LTP that includes the request identifier and a status indicator. The PCI device can use the status indicator and the request identifier to produce a CQE that is placed on a NVMe CQ associated with the SQ.

Methods and systems for providing a virtualized NVMe over fabric service

A network appliance can have an input port that can receive network packets at line rate, two or more ingress queues, a line rate classification circuit that can place the network packets on the ingress queues at the line rate, a packet buffer that can store the network packets, and a sub line rate packet processing circuit that can process the network packets that are stored in the packet buffer. The line rate classification circuit can place a network packet on one of the ingress queues based on the network packet's packet contents. A buffer scheduler can select network packets for processing by a sub line rate packet processing circuit based on the priority levels of the ingress queues.

Methods and systems for line rate packet classifiers for presorting network packets onto ingress queues

Certain tasks related to processing layer 7 (L7) data streams, such as HTTP data streams, can be performed by an L7 assist circuit instead of by general-purpose CPUs. The L7 assist circuit can normalize URLs, Huffman decode, Huffman encode, and generate hashes of normalized URLs. A L7 data stream, which is reassembled from received network packets, includes an L7 header. L7 assist produces an augmented L7 header that is added to the L7 data stream. The CPUs can use the augmented L7 header, thereby speeding up processing. On the outbound path, L7 assist can remove the augmented L7 header and perform Huffman encoding such that the CPUs can perform other tasks.

Methods and systems for layer 7 hardware assist and CPU task offloads

PCIe devices installed in host computers communicating with service nodes can provide virtualized and high availability PCIe functions to host computer workloads. The PCIe device can receive a PCIe TLP encapsulated in a PCIe DLLP via a PCIe bus. The TLP includes a TLP address value, a TLP requester identifier, and a TLP type. The PCIe device can terminate the PCIe transaction by sending a DLLP ACK message to the host computer in response to receiving the TLP. The TLP packet can be used to create a workload request capsule that includes a request type indicator, an address offset, and a workload request identifier. A workload request packet that includes the workload request capsule can be sent to a virtualized service endpoint. The service node, implementing the virtualized service endpoint, receives a workload response packet that includes the workload request identifier and a workload response payload.

Methods and systems for loosely coupled PCIe service proxy over an IP network

Methods and system for processing data in a programmable processing pipeline are disclosed. In an embodiment, a method for processing packets in a programmable packet processing pipeline is disclosed. The method involves processing data corresponding to a packet through a match-action pipeline of a programmable packet processing pipeline, and diverting the processing of data corresponding to the packet from the match-action pipeline to a processor core for out-of-pipeline processing.

Methods and systems for processing data in a programmable data processing pipeline that includes out-of-pipeline processing

Methods and devices for processing packets with reduced data stalls are provided. The method comprises: (a) receiving a packet comprising a header portion and a payload portion, wherein the header portion is used to generate a packet header vector; (b) producing a table result by performing packet match operations, wherein the table result is generated based at least in part on the packet header vector and data stored in a match table; (c) receiving, at a match processing unit, the table result and an address of a set of instructions associated with the match table; and (d) performing, by the match processing unit, one or more actions in response to the set of instructions until completion of the instructions, wherein the one or more actions comprise modifying the header portion, updating memory based data structure or initiating an event.

Network system including match processing unit for table-based actions

A multitude of data transfer queues can have data transfer operations that are scheduled for a processing circuit to perform. Some of the data transfer queues may submit so many or such large data transfer operations that others receive little or no attention. The situation can be resolved in the data plane via a processing circuit that performs the data transfer operations in conjunction with priority evaluation operations that can assign the data transfer queues to different scheduler priority classes. A scheduler can schedule data transfer operations based on the scheduler priority classes of the data transfer queues.

Methods and systems for adaptive network quality of service for latency critical applications

A configurable transaction filtering and logging circuit for on-chip communications within a semiconductor chip can store filter patterns. The filter patterns can include an address range filter pattern. The circuit can monitor transactions carried by an on-chip connection fabric. The transactions can be configured to transfer data between a first core circuit and a second core circuit that are also implemented on the semiconductor chip. The circuit can execute one of a set of actions in response to detecting a transaction that matches one of the filter patterns. One of the actions can be logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.

Methods and systems for address based transaction filters for on-chip communications fabrics

Methods and systems for managing statistics in an I/O system are disclosed. Embodiments of the present technology may include a method for managing statistical data at an I/O system, the method including reading a statistic record from an array of statistic records according to a write request that is held in a register of a register interface. In some embodiments, the write request includes a data element. In some embodiments, the array of statistic records is stored in random access memory (RAM).

Methods and systems for hardware-based statistics management using a general purpose memory

Methods and apparatuses for a programmable IO device interface are provided. The apparatus may comprise: a first memory unit having a plurality of programs stored thereon, the plurality of programs are associated with a plurality of actions comprising updating memory based data structure, inserting a DMA command or initiating an event; a second memory unit for receiving and storing a table result, and the table result is provided by a table engine configured to perform packet match operations on (i) a packet header vector contained in a header portion and (ii) data stored in a programmable match table; and circuitry for executing a program selected from the plurality of programs in response to the table result and an address received by the apparatus, and the program is executed until completion and the program is associated with the programmable match table.

Programmable computer IO device interface

Methods and systems for memory resource allocation are disclosed. In an embodiment, a method for memory resource allocation involves reading a pool-specific configuration record from an array of memory mapped pool-specific configuration records according to a memory resource allocation request that is held in an address register of a memory mapped register interface, performing a memory resource allocation operation to service the memory resource allocation request, wherein performing the memory resource allocation operation involves interacting with a resource list according to a pointer in the pool-specific configuration record, advancing the pointer after the interaction, and updating the pointer in the pool-specific configuration record with the advanced pointer.

Methods and systems for hardware-based memory resource allocation

Methods and network interface modules for processing packet headers are provided. The method comprises: receiving a packet comprising a header and a payload; generating, using the header, an initial packet header vector (PHV); providing the initial PHV to a pipeline comprising a plurality of processing stages; and processing the initial PHV in the pipeline, wherein the processing comprises, for a current processing stage in the plurality of processing stages: receiving, by the current processing stage, an input PHV, wherein the input PHV (i) is the initial PHV or a modified version of the initial PHV and (ii) comprises one or more flits, and applying a feature to the input PHV to generate an output PHV, including increasing an initial length of the input PHV if the initial length is not sufficient to apply the feature.

Variable-length packet header vectors

Growing community of inventors

Los Altos, CA, United States of America

Michael Brian Galles