Nvidia Corporation

Intel Corporation

S3 Incorporation

Michael Brian Cox

Brian K Langendorf

Brad W Simeral

Gary D Hicok

Ziyad Sami Hakura

David G Reed

Henry Packard Moreton

David Brian Glasco

David Nister

Franck Diard

Jonah Matthew Alben

John R Zedlewski

Rev Lebaredian

Ruchi Bhargava

Ratin Kumar

Tony Tamasi

Gordon Grigor

Justin Ebert

Miguel Sainz

Greg Heinrich

Timo Roman

Phillip Smith

Clement Farabet

Claire Delaunay

Tony C Tam

Matthew Campbell

David Auld

Martin Hempel

Zachary Taylor

Mark Daly

John Stephen Montrym

Stephen Donald Lew

Nicholas P Wilt

Sangmin Oh

Joachim Pehserl

Jen-Hsun Huang

Dong-Ying Kuo

Michael J Shantz

Hans Jonas Nilsson

Curtis A Beeson

Chin Shih

Dinyar B Lahewala

Chin-Hsien Shih

Daniel Perrin

Richard Hough

Curtis Beeson

Aidin Ehsanibenafati

Peter Alexander Boonstoppel

Blanton Scott Kephart

In various examples, systems and methods are disclosed that perform sensor fusion using rule-based and learned processing methods to take advantage of the accuracy of learned approaches and the decomposition benefits of rule-based approaches for satisfying higher levels of safety requirements. For example, in-parallel and/or in-serial combinations of early rule-based sensor fusion, late rule-based sensor fusion, early learned sensor fusion, or late learned sensor fusion may be used to solve various safety goals associated with various required safety levels at a high level of accuracy and precision. In embodiments, learned sensor fusion may be used to make more conservative decisions than the rule-based sensor fusion (as determined using, e.g., severity (S), exposure (E), and controllability (C) (SEC) associated with a current safety goal), but the rule-based sensor fusion may be relied upon where the learned sensor fusion decision may be less conservative than the corresponding rule-based sensor fusion.

Combining rule-based and learned sensor fusion for autonomous systems and applications

In various examples, physical sensor data may be generated by a vehicle in a real-world environment. The physical sensor data may be used to train deep neural networks (DNNs). The DNNs may then be tested in a simulated environment—in some examples using hardware configured for installation in a vehicle to execute an autonomous driving software stack—to control a virtual vehicle in the simulated environment or to otherwise test, verify, or validate the outputs of the DNNs. Prior to use by the DNNs, virtual sensor data generated by virtual sensors within the simulated environment may be encoded to a format consistent with the format of the physical sensor data generated by the vehicle.

Training, testing, and verifying autonomous machines using simulated environments

A system is provided for monitoring and controlling program flow in an event-triggered system. A program (e.g., application, algorithm, routine, etc.) may be organized into operational units (e.g., nodes executed by one or more processors), each of which tasked with executing one or more respective events (e.g., tasks) within the larger program. At least some of the events of the larger program may be successively executed in a flow, one after another, using triggers sent directly from one node to the next. In addition, the system of the present disclosure may include a manager that may exchange communications with the nodes to monitor or assess a status of the system (e.g., determine when a node has completed an event) or to control or trigger a node to initiate an event.

Program flow monitoring and control of an event-triggered system

A system and method for an on-demand shuttle, bus, or taxi service able to operate on private and public roads provides situational awareness and confidence displays. The shuttle may include ISO 26262 Level 4 or Level 5 functionality and can vary the route dynamically on-demand, and/or follow a predefined route or virtual rail. The shuttle is able to stop at any predetermined station along the route. The system allows passengers to request rides and interact with the system via a variety of interfaces, including without limitation a mobile device, desktop computer, or kiosks. Each shuttle preferably includes an in-vehicle controller, which preferably is an AI Supercomputer designed and optimized for autonomous vehicle functionality, with computer vision, deep learning, and real time ray tracing accelerators. An AI Dispatcher performs AI simulations to optimize system performance according to operator-specified system parameters.

Systems and methods for computer-assisted shuttles, buses, robo-taxis, ride-sharing and on-demand vehicles with situational awareness

In various examples, physical sensor data may be generated by a vehicle in a real-world environment. The physical sensor data may be used to train deep neural networks (DNNs). The DNNs may then be tested in a simulated environment&#x2014;in some examples using hardware configured for installation in a vehicle to execute an autonomous driving software stack&#x2014;to control a virtual vehicle in the simulated environment or to otherwise test, verify, or validate the outputs of the DNNs. Prior to use by the DNNs, virtual sensor data generated by virtual sensors within the simulated environment may be encoded to a format consistent with the format of the physical sensor data generated by the vehicle.

A digital camera includes an image optimization engine configured to generate an optimized image based on a raw image captured by the digital camera. The image optimization engine implements one or more machine learning engines in order to select rendering algorithms and rendering algorithm arguments that may then be used to render the raw image.

System and method for optimizing image quality in a digital camera

A method, an integrated circuit and a system for implementing a secure chain of trust is disclosed. While executing secure boot code in a secure boot mode, less-secure boot code may be authenticated using a secret key. A secure key may also be calculated or generated during the secure boot mode. After control is turned over to the authenticated less-secure boot code, at least one application may be authenticated using the secure key. Once authenticated in the less-secure boot mode, the application may be executed by the programmable integrated circuit. In this manner, a secure chain of trust may be implemented for the programmable integrated circuit.

Method and system for implementing a secure chain of trust

A method, system on a chip, and computer system for generating more robust keys which utilize data occupying relatively small die areas is disclosed. Embodiments provide a convenient and effective mechanism for generating a key for use in securing data on a portable electronic device, where the key is generated from repurposed data and a relatively small amount. A multi-stage encryption algorithm may be performed to generate the key, where the first stage may include encrypting the secure data, and the second stage may include encrypting the result of a logical operation on the encrypted secure data with a unique identifier of the portable electronic device. A secret key may be used as the encryption key for each stage. The result of the second encryption stage may include the generated key which may be used to perform subsequent operations on the portable electronic device.

Method and system for generating a secure key

A method for providing access to hardware devices by a processor without causing conflicts with other processors included in a computer system. The method includes receiving a first address map from a first processor and a second address map from a second processor, where each address map includes memory-mapped input/output (I/O) apertures for a set of hardware devices that the processor is configured to access. The method further includes generating a global address map by combining the first address map and the second address map, receiving a first access request from the first processor and routing the first access request to a hardware device based on an address mapping included in the global address map. Advantageously, heterogeneous processors included in multi-processor system can access any hardware device included in the computer system, without modifying the processors, one or more operating systems executed by each processor, or the hardware devices.

Chipset support for binding and migrating hardware devices among heterogeneous processing units

A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map.

Chipset support for non-uniform memory access among heterogeneous processing units

A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list. The method further includes arbitrating access requests from each of the plurality of operating systems based on the permission lists and the virtual address maps.

Centralized device virtualization layer for heterogeneous processing units

Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.

System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message

One embodiment of the present invention sets forth a technique for reducing the copying of data between memory allocated to a primary processor and a coprocessor is disclosed. The system memory is aliased as device memory to allow the coprocessor and the primary processor to share the same portion of memory. Either device may write and/or read the shared portion of memory to transfer data between the devices rather than copying data from a portion of memory that is only accessible by one device to a different portion of memory that is only accessible by the other device. Removal of the need for explicit primary processor memory to coprocessor memory and coprocessor memory to primary processor memory copies improves the performance of the application and reduces physical memory requirements for the application since one portion of memory is shared rather than allocating separate private portions of memory.

Zero-copy data sharing by cooperating asymmetric coprocessors

A bridge is disclosed having a security engine to protect digital content at insecure interfaces of the bridge. The bridge permits cryptographic services to he offloaded from a central processing unit to the bridge. The bridge receives a clear text input from a central processing unit. The bridge encrypts the clear text input as cipher text for storage in a memory. The bridge provided the cipher text to a graphics processing unit.

Chipset security offload engine

Growing community of inventors

Menlo Park, CA, United States of America

Michael Brian Cox