Spansion Llc.

Advanced Micro Devices Corporation

Michael Brennan

Scott Allan Bell

Hiroyuki Kinoshita

Ning Cheng

Ashot Melik-Martirosian

Fred Cheung

Kyunghoon Min

Mark W Randolph

Hidehiko Shiraiwa

Timothy J Thurgate

Yi He

Jean Y Yang

Rinji Sugino

Jean Yee-Mei Yang

Jaeyong Park

Satoshi Torii

David H Matsumoto

Ming-Sang Kwan

Vidyut Gopal

A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

Method for forming narrow structures in a semiconductor device

Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.

Flash memory devices and methods for fabricating same

An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.

Buried word line memory integrated circuit system

Flash memory devices and methods for fabricating the same

A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.

Memory device protection layer

The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.

Variable salicide block for resistance equalization in an array

A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.

Method for improved planarization in semiconductor devices

A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.

Multiple dual bit memory integrated circuit system

Growing community of inventors

Campbell, CA, United States of America

Michael Brennan