Lam Research Corporation

Michael Bowes

Anand Chandrashekar

Tsung-Han Yang

Gang Liu

Michal Danek

Leonard Wai Fung Kho

Atashi Basu

David M Fried

Xing Zhang

Dongyao Li

Kapil Umesh Sawlani

Provided herein are methods and apparatuses for controlling uniformity of processing at an edge region of a semiconductor wafer. In some embodiments, the methods include providing a backside inhibition gas as part of a deposition-inhibition-deposition (DID) sequence.

Backside reactive inhibition gas

Methods for selective inhibition control in semiconductor manufacturing are provided. An example method includes providing a substrate including a feature having one or more feature openings and a feature interior. A nucleation layer is formed on a surface of the feature interior. Based on a differential inhibition profile, a nonconformal bulk layer is selectively formed on a surface of the nucleation layer to leave a region of the nucleation layer covered, and a region of the nucleation layer uncovered by the nonconformal bulk layer. An inhibition layer is selectively formed on the covered and uncovered regions of the nucleation layer. Tungsten is deposited in the feature in accordance with the differential inhibition profile.

Tungsten feature fill with inhibition control

Methods of depositing a tungsten nucleation layers that achieve very good step coverage are provided. The methods involve a sequence of alternating pulses of a tungsten-containing precursor and a boron-containing reducing agent, while co-flowing hydrogen (H2) with the boron-containing reducing agent. The H2 flow is stopped prior to the tungsten-containing precursor flow. By co-flowing H2 with the boron-containing reducing agent but not with the tungsten-containing precursor flow, a parasitic CVD component is reduced, resulting in a more self-limiting process. This in turn improves step coverage and conformality of the nucleation layer. Related apparatuses are also provided.

High step coverage tungsten deposition

Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.

Fill process optimization using feature scale modeling

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Scotts Valley, CA, United States of America

Michael Bowes