Ceva D.s.p. Ltd.

Michael Boukaya

Jeffrey Allan (Alon) Jacob (Yaakov)

Roy Glasner

Jeffrey Allan Jacob

Moshe Steinberg

Shai Shpigelblat

Yaakov Dekter

Eran Briman

Shpigelblat Shai

Dekter Yaakov

A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

System and method for using a branch mis-prediction buffer

A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.

On-the-fly permutation of vector elements for executing successive elemental instructions

A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units with access to the register file.

Processor core interface for providing external hardware modules with access to registers of the core and methods thereof

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Raanana, Israel

Michael Boukaya