International Business Machines Corporation

Michael Billeci

Timothy John Slegel

Christian Jacobi

Fadi Y Busaba

Anthony Saporito

Khary J Alexander

Chung-Lung K Shum

James J Bonanno

Adam B Collura

Bruce C Giamei

Jane Helen Bartik

Douglas G Balazich

Lisa Cranton Heller

Mark S Farrell

Brian David Barrick

Gregory William Alexander

David S Hutton

Patrick M West, Jr

Bruce A Wagar

Donald G O'Brien

Eric M Schwarz

Brian Robert Prasky

Charles Franklin Webb

Martin Recktenwald

Phil C Yeh

Lee Evan Eisen

John G Rell, Jr

Timothy Gerard McNamara

David Andrew Schroter

Uwe Brandt

Timothy J Siegel

Jang-Soo Lee

David Allan Webber

Ching-Lung L Tong

Vimal M Kapadia

Timothy J Slegal

Embodiments relate to speculative branch handling for transaction abort. An aspect includes detecting a beginning of a current execution of a transaction. Another aspect includes, based on detecting the beginning of the transaction, disabling speculative execution based on branch prediction of an initial branch instruction of the transaction, wherein the initial branch instruction branches to two possible paths, and wherein a first path of the two possible paths comprises an abort handler. Another aspect includes disabling updating of a history table for the initial branch instruction.

Speculative branch handling for transaction abort

Uncorrectable memory errors in pipelined central processing units. A processor core may be connected to a memory system and it may include a processor cache. In response to determining an uncorrectable error in data stored in the memory system, the address of a memory location of the uncorrectable error is stored in an address buffer and a recovery procedure is performed for the processor core. When fetching data from a memory location and if it is determined that the address of this memory location is stored in the address buffer, the content of a cache line related to the address is moved into a quarantine buffer of the processor core. When detecting an error in the data of the moved cache line, a repair procedure for the data of this address is triggered.

Uncorrectable memory errors in pipelined CPUs

In one embodiment, a computer-implemented method includes requesting, by a first processor thread of a computer processor, access to exception tracking logic. The exception tracking logic is accessible by a plurality of processor threads. The first processor thread receives access to the exception tracking logic. The first processor thread executes a process in slow mode. Based on detecting an exception in slow mode, the first processor thread stores, in the exception tracking logic, exception information about the exception. The exception information is copied from the exception tracking logic to a set of external registers outside the exception tracking logic. The exception tracking logic is released to allow access to the exception tracking logic by other processor threads of the plurality of processor threads.

Sharing program interrupt logic in a multithreaded processor

Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.

Method and system for measuring the performance of a computer system on a per logical partition basis

A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.

Program status word dependency handling in an out of order microprocessor design

A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical register associated with the dispatched instruction has occurred. In this regard, the logical register lookup searches within at least one register mapper from a group of register mappers, including an architected register mapper, a unified main mapper, and an intermediate register mapper. A single hit to the logical register is selected among the group of register mappers. If an instruction having a mapper entry in the unified main mapper has finished but has not completed, the mapping contents of the register mapper entry in the unified main mapper are moved to the intermediate register mapper, and the unified register mapper entry is released, thus increasing a number of unified main mapper entries available for reuse.

Intermediate register mapper

A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.

Supporting partial recycle in a pipelined microprocessor

A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

Collecting computer processor instrumentation data

A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

Processor error checking for instruction data

A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.

Reduced overhead address mode change management in a pipelined, recycling microprocessor

A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register from being overwritten by a software update.

System, method and storage medium for controlling asynchronous updates to a register

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Poughkeepsie, NY, United States of America

Michael Billeci