Advanced Micro Devices Corporation

Globalfoundries Inc.

Ati Technologies Ulc

Advanced Micro Device, Inc.

Michael Bienek

Larry David Hewitt

Gamal Refai-Ahmed

Michael Zhouying Su

Bryan Black

Dales Morrison Kent

Victor F Andrade

Seth Prejean

Joseph R Siegel

Randal L Posey

Michael C Braganza

Ravi Ramaswami

Huining Liu

Ronnie Brandon

A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

Semiconductor chip with thermal interface tape

Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.

Method and apparatus to achieve more level thermal gradient

A device is provided for detecting temperature-induced delays in a combinational logic path. A signal at the output of the logic path is latched at a first latch using a primary clock signal. The primary clock signal is delayed by a delay element to provide a delayed clock signal. The output of the logic path is latched at a second latch using the delayed clock signal. The delay element delays the clock signal by an amount that indicates the occurrence of an over-temperature condition at the logic path. A comparator compares the data latched at the first latch to the data latched at the second latch and provides an error signal indicative of an over-temperature condition if the first and second latch contain different data values.

Over temperature detection apparatus and method thereof

An integrated circuit includes a first temperature sensing device providing an indication of a sensed temperature, a correlation oscillator circuit positioned adjacent to the first temperature sensing device, a plurality of other oscillator circuits, and storage locations storing calibration factors associated with at least the first temperature sensing device and the plurality of other oscillator circuits. A temperature calculation circuit determines temperatures of various locations in the integrated circuit. Each of the temperatures is determined according to an oscillation frequency of a respective one of the other oscillators, the oscillation frequency of the correlation ring oscillator, the temperature of the first temperature sensing device, and one or more stored calibration factors.

Zoned thermal monitoring

A method and apparatus for conducting built-in self-timing tests. In one embodiment, a method for conducting timing tests includes selecting one or more I/O pairs (each I/O pair including a driver and a receiver) into a loop of a ring oscillator, the ring oscillator including an odd number of inverters. The ring oscillator is coupled to a measurement circuit configured to measure delay time in the loop. After initiating operation of the ring oscillator, the delay time through the loop can be measured. Selection circuits may be used to selectively enable or bypass individual I/O pairs in the loop of the ring oscillator. This selective bypassing may allow timing measurements for individual I/O pairs.

Built-in self timing test method and apparatus

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Austin, TX, United States of America

Michael Bienek