Infineon Technologies Ag

Pmdtechnologies Ag

Qimonda Ag

Infineon Technologies Richmond, LP

Infineon Ag

Infineon Technology Ag

Michael Bernhard Sommer

Gerhard Enders

Thomas Hein

Stefan Dietrich

Patrick Heyne

Torsten Partsch

Christian Weis

Thilo Marx

Michael Bollu

Fabien Funfrock

Hans-Joachim Schulze

Anton Mauder

Roland Rupp

Thomas Nirschl

Guenther Ruhl

Helmut Fischer

Jan Otterstedt

Wolfgang Lehnert

Hermann Gruber

Rudolf Berger

Christian Peters

Wolf Allers

Raimund Foerg

Sabine Kieser

Jens Prima

Michael Markert

Günter Gerstmeier

Karsten Kellermann

Christian Rottmair

Henning Feick

Dirk Offenberg

Peter Schr&ouml;gmeier

Stefano Parascandola

Peter Schroegmeier

Christian Stocken

Rory Dickman

Matthias Franke

Robert Roessler

Helmut Schneider

Florian Schamberger

Joachim Schnabel

Joerg W Wohlfahrt

Ulrich Zimmermann

Rainer Florian Schnabel

Andreas Baenisch

Dieter Rathei

Jürgen Lindolf

Jochen Kallscheuer

Robert Petter

Mark E Luzar

Andreas Huber

Christoph Kamerow

Babatunde Ashiru

Thomas S Taylor

Luis G Andrade

Sabine Sch&ouml;niger Kieser

An optical sensor device configured to detect a time of flight of an electromagnetic signal includes a semiconductor substrate having a main surface and a conversion region configured to convert at least a fraction of the electromagnetic signal into photo-generated charge carriers; a first control electrode formed in a trench extending from the main surface into the semiconductor substrate; a second control electrode disposed directly or indirectly on the main surface; a control circuit configured to apply a varying first potential to the first control electrode and to apply a varying second potential to the second control electrode, where the varying second potential has a fixed phase relationship to the first varying potential, to generate electric potential distributions in the conversion region to direct the photo-generated charge carriers; and a readout node arranged in the semiconductor substrate and configured to detect the directed photo-generated charge carriers.

Optical sensor device with deep and shallow control electrodes

An optical sensor device configured to detect a time of flight of an electromagnetic signal includes a semiconductor substrate with a conversion region configured to convert at least a portion of the electromagnetic signal into photo-generated charge carriers. A deep control electrode is formed in a trench extending into the semiconductor substrate. The deep control electrode extends deeper into the semiconductor substrate than a shallow control electrode. A control circuit is configured to apply to the deep control electrode and to the shallow control electrode varying potentials having a fixed phase relationship to each other, to generate electric potential distributions in the conversion region, by which the photo-generated charge carriers in the conversion region are directed. The directed photo-generated charge carriers are detected at at least one readout node.

The present invention provides a time-of-flight sensor () including at least one time-of-flight pixel () for demodulating a received modulated light beam (Sp), wherein the time-of-flight pixel () comprises at least two integrating nodes (Ga, Gb) and the integration nodes (Ga, Gb) are connected to a device () for charge compensation, wherein the charge compensation device () comprises at least two SBI input transistors (M, M) which at a potential (Ua, Ub) of the integration nodes (Ga, Gb) which according to the amount exceeds an SBI threshold value (U) drive SBI current transistors (M, M) such that at both integration nodes (Ga, Gb) a compensating current (i) of the same level flows, wherein the source terminals of the SBI-current transistors (M, M) are not connected to a supply voltage (U) but are connected to a working voltage (U, U) (FIG.).

Light propagation time sensor with a charge compensation device

Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

Semiconductor device with channel switching structure and method of making same

A composite wafer is manufactured by providing a carrier wafer including graphite and a protective layer, forming a bonding layer, and bonding the carrier wafer to a semiconductor wafer through the bonding layer.

Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core

A memory cell including a substrate with a protruding portion, the protruding portion having a side wall and a bottom, an upper doped region connected to a bit line, a lower region being closer to a bottom of the protruding portion than the upper region, a substrate contact, a control element configured to control a current flow between the lower region and the substrate contact, and a wordline portion, a first insulator near the wordline portion, a floating gate near the wordline portion, and a second insulator between the floating gate and the side wall of the protruding portion, wherein the wordline portion and the floating gate are arranged so that the channel is generate-able in the substrate near the side wall between the upper doped region and the lower region.

Memory cell

According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.

One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.

Method of operating phase-change memory

Semiconductor device and method for making same

One or more embodiments are related to a method of operating a phase-change memory array, including: providing the phase-change memory array, the phase-change memory array including a phase-change memory element in series with an access device between a first address line and a power line; causing a first current through the memory element from the first address line to the power line; and causing a second current through the memory element from the power line to the first address line.

A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.

Semiconductor device, a method of using a semiconductor device, a programmable memory device, and method of producing a semiconductor device

A chip with a chip plane includes a functional area, a contact structure vertical with respect to the chip plane for connecting the functional area, which includes a conductive material, which has a predetermined length, and a vertical dummy-contact structure, which extends vertically into the functional area and which has an electrically conductive material and an insulation layer, the insulation layer being formed so that a current flow from an upper end of the dummy-contact structure to the functional area is prevented.

Chip with a vertical contact structure

A monitor structure for monitoring a change of a memory content in a memory field of a non-volatile memory comprising a reference transistor in the memory field and a monitor transistor. The monitor transistor and the reference transistor comprise a common floating gate. Moreover, the memory field is arranged in a first well, and the monitor transistor in a second well. The first well and the second well are of different doping types.

Monitor structure for monitoring a change of a memory content

A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

Data retention monitor

Growing community of inventors

Reubling, Germany

Michael Bernhard Sommer