Lsi Logic Corporation

Qualcomm Incorporated

Michael Bernard Smith

Michael J Tresidder

Etan Gur Cohen

System and method for load-balancing a plurality of transmission media. A first plurality of packets of a first stream may be transmitted to a second device on a first transmission medium. It may be determined that current medium utilization of the first transmission medium exceeds a first threshold. The first stream may be selected for transmission on both of the first transmission medium and a second transmission medium based on said determining that current medium utilization of the first transmission medium exceeds the first threshold. A second plurality of packets of the first stream may then be transmitted to the second device using both the first transmission medium and the second transmission medium. A first portion of the second plurality of packets may be transmitted on the first transmission medium and a second portion of the second plurality of packets may be transmitted on the second transmission medium.

Packet-based aggregation of data streams across disparate networking interfaces

To vigorously test synchronization logic and protocols in a digital circuit design, a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits. The synchronization logic model is inserted into a software description of the design so that simulation will reveal faulty assumptions in the synchronization protocol. Additionally, where a non-synchronized signal crosses from one clock domain to another clock domain in an asynchronous digital design, a transition on the non-synchronized signal triggers an &ldquo;X&rdquo; value window on the signal for a selected period relative to the receiving clock period, so that simulation will fail if the receiving logic samples the signal value during the &ldquo;X&rdquo; value window. These techniques aid in effective testing of the design.

Testing synchronization circuitry using digital simulation

A method and device for automatically verifying results of a simulation is disclosed. External stimuli are applied to a device under test and observed output is generated in response thereto. The observed output is applied to a non-cycle accurate model of the device comprising procedures which simulate significant events corresponding to the significant events of the observed output. Verification conditions are set according to the aspects of the device under test which are being tested and the verification conditions are applied to the output from the non-cycle accurate model. The verification conditions are associated with a procedure of the model such that the verification condition is verified before or after execution of the procedure. In addition, the verification conditions may be executed at the end of the simulation to ensure that all events which should have occur, have occurred. It is possible to control which observed outputs are applied to the model so that a user can interactively observe changes in the state of the model. If a verification condition is not satisfied, an error flag is raised marking a part of the model output which did not satisfy a verification condition.

Method and device for automatic simulation verification

A device and method to control a node within a network is disclosed. The node can have any number of ports N where N is an integer greater than one. The device has N-port modules, corresponding to the number of ports in the node, each port module associated with one port for controlling reception and transmission of information through the associated port. The port modules are substantially identical and the device can be manufactured by replicating N-port modules, one port module for each port. The port modules have a priority within the node. The priority can be created by connecting the port modules in a daisy chain configuration. The port module having the highest priority compares the unique identifier of the node with the unique identifier being received by the port associated with the highest priority port module. The results of this comparison are sent to the next highest priority port module. The port modules compare, in a predetermined priority, the unique identifier being received by the associated port with the unique identifier having been sent by the previous port modules. This continues until all of the port modules have agreed upon a unique identifier which satisfies a set of predetermined conditions. Once the port modules have all determined that an identically unique identifier satisfies the predetermined conditions, the device disables ports which are receiving this identical unique identifier from the root node until only one port in the node is receiving this unique identifier from the root node.

N-port algorithm for disabling a node within a network during reset

An apparatus and method implementing an algorithm for determining the most likely least recently used cache line in a cache so that this cache line can be written back to main memory. This algorithm is implemented on a bus control unit bridging a 50 Mhz multi-processor interconnect bus with a 33 Mhz peripheral component interconnect bus through an asynchronous interface. All data being transferred between the multi-processor interconnect bus and the peripheral component interconnect bus must pass through the input/output cache on the bus control unit. The algorithm determines a unique locating path to the last used cache lines and from this determines a unique locating path to a memory location which likely contains a least recently used cache line which can then be written back to main memory. Each memory location is identified by a unique locating path which passes through a nodal tree. Each node on the lowest level of nodes is associated with two memory locations, and, each pair of nodes is associated with one node on a next high level of nodes. Each node is associated with a bit in a register which is used to identify and record the unique path through the nodes of the cache lines being used and stored. The unique locating path to the memory location with the cache lines to be written back to memory, or otherwise evicted, is determined based on the stored value of bits.

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Etobicoke, Canada

Michael Bernard Smith