Emc Corporation

Michael Bermingham

John K Walton

Christopher S MacLellan

Kendell Alan Chilton

Daniel Castel

William F Baxter

James Marriott Guyer

Rizwan Sheikh

Mark J Halstead

Haim Kopylovitz

Steven T McClure

Brett D Niver

Ofer Michael

Robert DeCrescenzo

James M McGillis

Described are techniques for selective data replication. Cached data is replicated if it is characterized as critical. Critical data may include data associated with a write I/O operation. Cache locations are selected for replicated data so that a first location is mapped to a first memory board and a second location is mapped to a second memory board. Data for a read operation is not replicated in cache. Other non-cache data that is critical and thus replicated includes metadata. Cache locations for data of read and write I/O operations are selected dynamically at the time the I/O operation is made from the same pool of cache locations.

Method, computer readable medium, and data storage system for selective data replication of cached data

A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.

Data system having a virtual queue

A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.

Data storage system having shared resource

A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives. The system includes a cache memory manager having therein a memory for storing a map maintaining a relationship between data stored in the cache memory and data stored in the disk drives. The cache memory manager provides an interface between the host computer, the bank of disk drives and the cache memory for determining for the directors whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. With such an arrangement, the cache memory in the data transfer section is not burdened with the task of transferring the director messaging but rather a messaging network is provided, operative independent of the data transfer section, for such messaging thereby increasing the operating bandwidth of the system interface. Further, the cache memory is no longer burdened with the task of evaluating whether data to be read from the disk drives, or data to be written to the disk drives, resides in the cache memory. The cache memory manager, plurality of front end directors, plurality of back end directors and cache memory are interconnected through a packet switching network.

Data storage system having cache memory manager with packet switching network

A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.

Systems and methods which utilize parity sets

A method and apparatus for hot-plugging circuit boards having lower voltage logic devices into a higher voltage backplane in a manner that minimizes overvoltage stress during system power-up, or during a lower voltage power failure. The method and apparatus ensures that the lower voltage device(s') power input reaches at least a nominal input level before any other inputs of the device are driven to a level greater than or equal to an expected input level. Dedicated output pins on lower voltage logic device(s) are configured to issue a control output signal for enabling higher voltage devices. Output enable terminals for the higher voltage parts, which are connected to respective control outputs from a lower voltage device, are normally in a disabled state as a function of pull-up or pull-down circuitry. A respective control output signal is provided for each higher voltage device output enable to enable the outputs of the higher voltage device when the voltage supply input to the lower voltage device is at substantially full voltage.

Method and apparatus for hot-plugging circuit boards having low voltage

An optimized memory refresh scheme controls and reduces instantaneous power consumption and power-related noise during DRAM refresh. In the optimized refresh implementation the DRAM is refreshed using a selectable overlap Column Address Select (CAS) before Row Address Select (RAS) refresh mode. A refresh interface between a host port and the memory system is over two bussed signals comprised of a Refresh Enable signal (Refresh.sub.-- Enable) and a Refresh Strobe pulse train (Refresh.sub.-- Strobe). Refresh.sub.-- Enable is issued by the host port to define a refresh operation. Refresh.sub.-- Strobe is a pulse train generated by the host port which is used as a clock for a sequential refresh sequencer. A refresh sequencer issues selectably timed column address refresh and row address refresh signals according to which the memory banks can all be selectably refreshed substantially in parallel, or with a predetermined selected level of overlap. Optimized skewing can be implemented to minimize the time for refresh. Refreshing of different memory banks can be selectably overlapped to provide acceptable current and noise profiles during refresh.

Method and apparatus for refreshing a non-clocked memory

A buffer memory includes at least one memory including a plurality of memory locations, and at least one write-control circuit. When data is written to one of the plurality of memory locations, the at least one write-control circuit causes at least one bit of validation information to be written to the at least one memory to indicate that the data written to the one of the plurality of memory locations is valid. In response to data being read from the one of the plurality of memory locations, the at least one write-control circuit causes the at least one bit of validation information to be overwritten to indicate that the data stored in the one of the plurality of memory locations is invalid. In another embodiment, a method for operating a buffer memory including a plurality of memory locations includes steps of: (a) when data is written to one of the plurality of memory locations, storing at least one bit of validation information in the buffer memory indicating that the data written to the one of the plurality of memory locations is valid; and (b) in response to the data being read from the one of the plurality of memory locations, overwriting the at least one bit of validation information to indicate that the data stored in the one of the plurality of memory locations is invalid.

Method and apparatus for detecting errors in the writing of data to a

A modular memory array configuration uses a combinatorial decoding device (decoder), instead of straight buffering, to effect optimal delivery of control and address signals. Each port accessing memory on the array drives a single copy of address and control signals, plus bank select signals, over a shared interface to the decoder. Bank select controls the decoder which drives the address and control to only the accessed bank. Address and control signals to all banks but the accessed bank, are pulled up (inactive) with resistors on the memory array. For N banks, log2 N bank select bits are needed. The decoder device does not need to be clocked and therefore avoids problems associated with selecting between and providing asynchronous or redundant clocks for a multi-ported shared memory with ports independent of and asynchronous to one another. Output glitches on the output control signals are avoided by having the port controller performing a memory access first switch the bank select signals while all other inputs are stable and logically inactive. The bank select value is maintained for the duration of the memory access, while the other inputs may switch. Pin requirements for port controllers and memory array connectors are minimized. Simultaneous switching output noise on both the port controllers and memory array address/control drivers is also minimized.

Modular memory system with shared memory access

A storage apparatus including a memory; a first buffer into which data words are read from said memory; and a word selector receiving on a first input data words from the buffer and on a second input data words from another source, and producing on an output for storage back into the memory data words that are selected from the first and second inputs to the word selector.

Growing community of inventors

Framingham, MA, United States of America

Michael Bermingham