U.S. Philips Corporation

Michael Behrens

Peter Hessler

Bernd Selbach

Manfred Schmidt

Ludwig Bayer

Michael Siebke

In an arrangement for combining at least two source signals to a multiplex signal, source signals from independently operating source modules are transmitted to a multiplex module in which they are combined into the multiplex signal in a predetermined manner. An orderly operation of the modules is ensured in that each source module includes at least a memory, a write counter and a read counter. The counters are arranged to operate independently of each other and to generate the addresses when the data are being written into and read from the memory. The arrangement includes a memory for storing the frame-structured source signals at the start of a new frame starting at a predetermined initial address of the memory and for marking the memory address of the end of the frame with a marking bit. The arrangement also includes read logic for reading the source signals from the memory of the source modules under control of a clock signal supplied by the multiplex module, and for transmitting the source signals to the multiplex module. Each source module is arranged to supply a reset signal after the marked address has been read during reading of a frame. The arrangement is adapted to set the read counters of all source modules to the predetermined initial address when the reset signal is eliminated.

Multiplexer for at least two independently operating signal sources

A sampling circuit for sampling a binary signal and producing an output signal representative of a particular sample of the binary signal. The sampling circuit includes a storage unit to store successive samples of the binary signal which are acquired in a time interval shorter than the time period between two subsequent transitions of the binary signal. A test unit is coupled to the storage unit and is operative to perform the following operations: testing a plurality of successive samples, supplied by the storage unit, for being functionally identical to one another; producing an output signal representative of any of the plurality of successive samples upon detecting the identity; upon detecting the absence of identity among the plurality of samples: testing a further plurality of successive samples, supplied by the storage unit, for being functionally identical to one another; producing an output signal representative of any of the further plurality of successive samples upon detecting identity among the further plurality of samples; and upon detecting the absence of identity among the further plurality of successive samples, producing an output signal representative of a predetermined substitute.

Circuit arrangement for sampling a binary signal

A circuit arrangement compensates for changes of pulse-duration in a binary signal. These changes of pulse-duration are the consequence of parasitic reactances in the signal path of the binary signal. A compensating circuit, which owing to its simplicity is particularly suitable for integrated circuits, is characterized in that a signal is inverted by an input inverter (I1) after it has passed through the signal path, then passes through a copy (NA) of the signal path, and is inverted once again by an output inverter (I1). If the signal path and its copy are integrated on a single chip, an adjustment of the copy (NA) need not be performed. Particularly advantageous--because of its cost-effectiveness--is the implementation of the above circuit in switching networks which are realized as integrated circuits. For each output of the switching network only a single copy (NA) will then be necessary.

Circuit arrangement which compensates for pulse-duration changes in a

A circuit arrangement for channel-specific processing of a multi-channel input signal which may consist of two types of encoded signals, a first type wherein all channel signals are encoded by a bit-oriented method (e.g., delta modulation) and a second type wherein all channel signals are encoded by a character-oriented method (e.g., PCM). An interface process (SSP), to which the input signal is applied, is coupled to a bidirectional interface (BIS) for signals of the first type and which is controllable by means of write and read addresses, and is also coupled to at least two such bidirectionally controllable interfaces (BI0, BI1, . . . BI7) for signals of the second type. The latter interfaces are respectively coupled to respective transcoder processors (AP0, AP1, . . . AP7). One or more data outputs of the interface (BIS) for signals of the first type are respectively coupled to respective ones of the transcoder processors (AP0, AP1, . . . AP7). The transcoded channel signals produced by such processors are transmitted via the interfaces (BIS, BI0, . . . BI7) to the interface processor (SSP), which combines them into a multi-channel output signal.

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Nuremberg, Germany

Michael Behrens