Intel Corporation

Michael Behar

Yaniv Fais

Tomer Bar-On

Amit Bleiweiss

Jeremie Dreyfuss

Lev Faivishevsky

Jacob Subag

Gal Leibovich

Itamar Ben-Ari

Guy Jacob

Tomer Schwartz

Uzi Sarel

Ehud Cohen

Amitai Armon

Roni Rosner

Moshe Maor

Galina Ryvchin

Zigi Walter

Oren Agam

Yahav Shadmiy

Bharat Daga

Ajit Singh

Eyal Yaacoby

Ronen Gabbai

Raanan Yonatan Yehezkel Rohekar

Israel Diamand

Oz Shitrit

Dmitri Vainbrand

Ravi Venkatesan

Shlomi Shua

Edward Thomas Grochowski

Ohad Falik

Alexander Gendler

Ilan Pardo

Oren Ben-Kiki

Dror Markovich

Daniel David Ben-Dayan Rubin

Shlomi Alkalay

Henrietta Bezbroz

Amital Armon

Ashutosh Parkhi

In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

Real time context dependent deep learning

Methods, apparatus, systems and articles of manufacture are disclosed to configure heterogenous components in an accelerator. An example apparatus includes a graph compiler to identify a workload node in a workload and generate a selector for the workload node, and the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.

Methods and apparatus to configure heterogenous components in an accelerator

Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

Compression for deep learning in case of sparse values mapped to non-zero value

A convolutional neural network (CNN) accelerator, including: a CNN circuit for performing a multiple-layer CNN computation, wherein the multiple layers are to receive an input feature according to an input feature map (IFM) and a weight matrix per output feature, wherein an output of a first layer provides an input for a next layer; and a mapping circuit to access a three-dimensional input matrix stored as a Z-major matrix; wherein the CNN circuit is to perform an inner-product direct convolution on the Z-major matrix, wherein the direct convolution lacks a lowering operation.

Inner product convolutional neural network accelerator

Methods, apparatus, systems and articles of manufacture are disclosed that enable out-of-order pipelined execution of static mapping of a workload to one or more computational building blocks of an accelerator. An example apparatus includes an interface to load a first number of credits into memory; a comparator to compare the first number of credits to a threshold number of credits associated with memory availability in a buffer; and a dispatcher to, when the first number of credits meets the threshold number of credits, select a workload node of the workload to be executed at a first one of the one or more computational building blocks.

Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload

In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

Multiply-accumulate '0' data gating

In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.

Shared read&#x2014;using a request tracker as a temporary read cache

Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.

Methods and apparatus to implement multiple inference compute engines

Growing community of inventors

Zichron Yaakov, Israel

Michael Behar