Philips Electronics North America Corporation

Koninklijke Philips Corporation N.v.

U.S. Philips Corporation

North American Philips Corporation

U.S. Philips Electronics North America Corporation

Michael Bakhmutsky

Karl R Wittig

Viktor L Gornstein

Mikhail Tsinberg

Carlo Basile

Alan P Cavallerano

Johan Gerard Janssen

Howard B Pein

Egbert G T Jaspers

A method of correcting a video signal includes retrieving a correction data from a respective one multiple memory devices; reordering the correction data to a predetermined order for a particular segment; and interpolating multiple correction data so that all pixels in the particular segment have a corresponding one of the correction data. An apparatus for correcting video comprises multiple memory devices, each having multiple correction data; a cross-bar switch that reorders at least some of the data to a predetermined order for a particular segment; and an interpolator that calculates multiple interpolated correction data. One of the correction data corresponds to one of multiple pixels in the segment.

Color non-uniformity correction method and apparatus

A block matching motion estimation algorithm uses reduced precision data when comparing pictures in the block to be compressed with pictures in a reference block. This yields a plurality of best match candidates. The average of the best match candidates, excluding those candidates which fall outside a predetermined cluster boundary, is determined and then a second search is performed focused on this average. In this way, the amount of hardware for the block matching algorithm is decreased and the speed of its operation is enhanced.

Block matching motion estimation using reduced precision clustered predictions

A contrast control and clipping device is configured to determine a maximum range of enhancement that may be applied to each pixel for picture sharpness enhancement. This maximum range is used to limit the enhancement that is determined by the conventional convolution kernel and gain control modules. Preferably, the maximum range is independent of the determined convolution value, thereby minimizing the bandwidth requirements among the modules used for picture sharpness enhancement. The reduced bandwidth requirement allows for an efficient partitioning of tasks between hardware and software embodiments, and eases the overall system design task. In a multi-media application, the amount of data that is transferred between the processor and sub-components is substantially reduced, and the efficient partitioning facilitates parallel processing. The maximum range of enhancement is determined based on the pixel values in the current field, using a computationally simple algorithm, thereby minimizing anomalies caused by temporal dependencies among the modules that are used for picture sharpness enhancement. Additionally, the sharpness enhancement is dynamically adjusted based on overall picture-level characteristics, including the average enhancement range, overall noise measures, and so on.

Adaptive clipping prevention for picture sharpness enhancement

A method for motion coding an uncompressed digital video data stream such as an MPEG-2 digital video data stream. The method includes the steps of comparing pixels of a first pixel array in a picture currently being coded with pixels of a plurality of second pixel arrays in at least one reference picture and concurrently performing motion estimation for each of a plurality of different prediction modes in order to determine which of the prediction modes is an optimum prediction mode determining which of the second pixel arrays constitutes a best match with respect to the first pixel array for the optimum prediction mode, and, generating a motion vector for the first pixel array in response to the determining step. The method is implemented in a device such as a motion estimation search system of a digital video encoder. In one embodiment, the method and device are capable of concurrently determining performing motion estimation in each of the six different possible prediction modes specified by the MPEG-2 standard.

Method of concurrent multiple-mode motion estimation for digital video

A method for determining a best match between a first pixel array in a picture currently being encoded and a plurality of second pixel arrays in a search region of a reference picture, wherein each of the first and second pixel arrays includes a plurality of rows and columns of individual pixel values. The method is designed to be performed in a motion estimation search engine of a digital video encoder, and includes the steps of producing a first orthogonal-sum signature of the first pixel array comprised of a set of horizontal sums representative of the sums of the individual pixel values of the rows of the first pixel array and a first set of vertical sums representative of the sums of the individual pixel values of the columns of the first pixel array; producing a plurality of second orthogonal-sum signatures for respective ones of at least selected ones of the plurality of second pixel arrays, each of the plurality of second orthogonal-sum signatures being comprised of a set of horizontal sums representative of the sums of the individual pixel values of the rows of a respective one of the second pixel arrays and a set of vertical sums representative of the sums of the individual pixel values of the columns of a respective one of the second pixel arrays; and, comparing the first orthogonal-sum signature with each of the second orthogonal-sum signatures in order to determine the best match between the first and second pixel arrays. In a disclosed embodiment, the first and second pixel arrays are either decimated or undecimated macroblocks having a structure defined by an MPEG standard, e.g., the MPEG-2 standard.

Motion estimation method using orthogonal-sum block matching

A method for determining a best match between a first pixel array in a picture currently being encoded and a plurality of second pixel arrays in a search region of a reference picture, wherein each of the first and second pixel arrays includes a plurality R of rows and a plurality C of columns of individual pixel values. The method includes the steps of providing a first full orthogonal-sum signature of the first pixel array comprised of a set of horizontal sums representative of the sums of the individual pixel values of the rows of the first pixel array and a first set of vertical sums representative of the sums of the individual pixel values of the columns of the first pixel array; providing a plurality of partial orthogonal-sum signatures for respective ones of the plurality of second pixel arrays, each of the plurality of partial orthogonal-sum signatures being comprised of a set of partial horizontal sums representative of the sums of the individual pixel values of a plurality M of the rows of a respective one of the second pixel arrays and a set of partial vertical sums representative of the sums of the individual pixel values of a plurality N of the columns of a respective one of the second pixel arrays, wherein M<R and N<C; concurrently computing a plurality of second full orthogonal-sum signatures for the respective ones of the plurality of second pixel arrays using the plurality of partial orthogonal-sum signatures; and, comparing the first full orthogonal-sum signature with each of the second full orthogonal-sum signatures in order to determine the best match between the first and second pixel arrays. In a presently preferred embodiment, M&equals;R&minus;1 and N&equals;C&minus;1; the set of partial horizontal sums is representative of the sums of the individual pixel values contained in N columns of R&plus;1 rows of an (C&plus;1)-by-(R&plus;1) pixel array that encompasses all of the second pixel arrays, and the set of partial vertical sums is representative of the sums of the individual pixel values contained in M rows of C&plus;1 columns of the (C&plus;1)-by-(R&plus;1) pixel array; the R&plus;1 rows and the C&plus;1 columns collectively comprise the (C&plus;1)-by-(R&plus;1) pixel array that encompasses all of the second pixel arrays; and, the M rows and N columns are centered in the (C&plus;1)-by-(R&plus;1) pixel array. Also disclosed is a device, e.g., a motion estimation search engine of a digital video encoder, that implements the method of the present invention.

Motion estimation method featuring orthogonal-sum concurrent multi matching

A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Pixel data storage system for use in half-pel interpolation

RAM-based search engine for orthogonal-sum block match motion estimation system

A controller for controlling the operation of a variable length decoder, which includes a coding protocol determination circuit for determining a coding protocol used in coding a digital data stream currently being decoded by the variable length decoder, and a configuration control circuit for automatically reconfiguring the variable length decoder into a selected one of a plurality of different possible decoding configurations, depending upon the determined coding protocol. Also disclosed is a controller for controlling the operation of a variable length decoder, which includes a code type determination circuit which determines a code type of a current code word currently being decoded by the variable length decoder, and a mode switching circuit which switches a mode of operation of the controller between a parallel decoding mode of operation and a tree-searching mode of operation, depending upon the determined code type of the current code word. Also disclosed is a code word value memory which can be used by a variable length decoder for decoding the values of the code words in the input digital data stream. The code word value memory is logically organized into a plurality of individually addressable pages, at least one of which is addressed by a first code prefix and includes individual code word values addressed by the first code prefix plus a sub-tree associated with at least one other code prefix, to thereby maximize memory utilization and minimize the required memory size.

Controller for a variable length decoder

A variable length decoder for decoding an input digital data stream which includes a plurality of variable length code words which are coded in accordance with any of a plurality of different coding standards. The variable length decoder includes an input circuit which receives the input digital data stream and produces a decoding window that includes a leading word aligned bit stream, and a decoding circuit which is configurable into any selected one of a plurality of different decoding configurations, depending upon which coding standard the input digital data stream is coded in accordance with, the decoding circuit being coupled to the leading word aligned bit stream for decoding the length and value of each code word in the input digital data stream. The variable length decoder further includes a programmable controller for controlling the operation of the variable length decoder in accordance with any of a plurality of different decoding protocols, depending upon the coding standard employed in coding the input digital data stream. The programmable controller determines which coding standard was employed in coding the input digital data stream, and then automatically configures the decoding circuit into the decoding configuration which is appropriate for decoding the input digital data stream, based upon this determination. The variable length decoder also includes a code word value memory which is used for decoding the values of the code words in the input digital data stream.

Universally programmable variable length decoder

A variable length decoder with adaptive acceleration in processing of an encoded input bit stream which includes an input section which receives the input bit stream and provides a decoding window that includes a sequence of bits which include one or more code words to be decoded at an output thereof. A code word length decoding section determines the combined length of a combination of two or more code words received from the input section in response to a first value of a control signal and generates a combined length signal representative of the determined combined length, and determines the length of an individual code word received from the input section in response to a second value of the control signal, and generates an individual code word length signal representative of the determined length of the individual code word. A computation loop section receives the combined length signal or the individual word length signal from the code word length decoding section and, in response thereto, shifts the decoding window to provide a new sequence of bits that include one or more additional code words to be decoded at the output of the input section. A code word value decoding section decodes the values of the combination of two or more code words provided by the input section in response to the first value of the control signal, and decodes the value of the individual code word in response to the second value of the control signal. A control section generates the control signal and controls the operation of the variable length decoder according to a decoding protocol (e.g., MPEG-2). The two or more code words of the combination of code words are part of a sub-grouped and cross-grouped set of code words of a selected group of M code words in the input bit stream whose bit lengths are .ltoreq. than a prescribed number N. Less than all possible combinations of the selected group of M code words are stored as entries in a look-up table, so that the total number of combinations of the selected group of M code words which are stored as entries in the look-up table is less than M.sup.2.

Variable length decoder with adaptive acceleration optimized by

A microblock-level partitioned digital HDTV video decoder for decoding a bit stream consisting of a series of macroblocks of digital video data which are coded in accordance with an MPEG or other predetermined digital compression code. The decoder includes a bit stream parser for identifying boundaries between the macroblocks and producing macroblock boundary information indicative of the identified boundaries, a bit stream formatter for combining the macroblock boundary information with the bit stream to produce a combined bit stream having successive multi-bit portions, a rate buffer for storing and sequentially outputting the successive multi-bit portions, first and second FIFO memories, and a FIFO controller for alternately write enabling the first and second FIFO memories in response to the macroblock boundary information. The FIFO memories thereby alternately store the successive macroblocks in the combined bit stream sequentially outputted from the rate buffer. First and second variable length decoders decode the successive multi-bit portions of the combined bit stream respectively stored in the first and second FIFO memories. A related method is also presented.

Macroblock-level partitioned HDTV video decoder and related method

A variable length decoder (VLD) for processing an input bit stream (e.g., MPEG video) which includes qualifying and non-qualifying types of variable length code words. The VLD includes an input circuit for receiving the input bit stream and providing a sequence of available input bits, a shifter circuit for providing a decoding window that includes one or more code words contained in the sequence of available input bits, a code word length decoding circuit for determining whether or not the decoding window contains a pair of qualifying code words, and for determining the combined length of the pair of qualifying code words and producing a combined length signal representative of the determined combined length, if the decoding window contains a pair of qualifying code words, and further, for determining the length of a leading code word contained in the decoding window and producing a leading word length signal representative of the determined length of the leading code word. The VLD also includes a computation loop circuit for generating a word pointer signal, in response to the combined length signal if it is determined that the decoding window contains a pair of qualifying code words, or otherwise, in response to the leading word length signal. The shifter circuit is responsive to the word pointer signal for shifting the decoding window across the sequence of available input bits. A related method is also disclosed.

High performance variable length decoder with two-word bit stream

A method for pair-match Huffman transcoding a Huffman-encoded bit stream (e.g., an MPEG digital video bit stream) which includes a plurality of qualifying and non-qualifying types of variable length original code words to be processed by a variable length decoder (VLD) with two-word bit stream segmentation, wherein the VLD has a decoding, window N bits wide. The method includes the steps of pair-match Huffman transcoding at least selected ones of the qualifying types of code words to produce corresponding transcoded code words in such a manner that the combined length of any pair of the transcoded code words is .ltoreq.N. A device for implementing this method, as well as a high-performance variable length decoder with two-word bit stream segmentation which utilizes this method, are also disclosed.

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Spring Valley, NY, United States of America

Michael Bakhmutsky