Sony Corporation

Michael B Shields

Barrett E Guisinger

Donald E Morgan

A system and method for performing error correction on an SFAT format video signal which has been encoded using an error correction code ECC2, and generating a video signal reconstructed from the error-corrected input signal. The error code preferably is a cross interleave Reed-Solomon code. In a preferred embodiment, the system is capable of reconstructing the output video signal so that it has either SFA or SFAT format. Since an SFAT signal includes duobinary encoded data in its active video areas, and thus may be doubly error encoded using two error correction codes (ECC1 and ECC2), the invention is capable of generating from such a doubly encoded signal an ECC1 error-encoded video signal, in SFA (or SFAT) format, which has been error-corrected using error code ECC2. This capability is particularly advantageous where the invention is embodied in a video disk mastering system or method. In a preferred embodiment, the invention also determines the error rate of the input signal and generates a report signal indicative of the input signal's detected error rate. A preferred embodiment of the invention performs both error correction and error detection on-line, in real time, and automatically.

System and method for performing error correction on still frame audio

A motor control method and apparatus employing a speed control loop and a phase control loop, each of which receives a clock signal (F.sub.-- TACH) indicative of the motor's measured phase and rotational frequency, and a synchronizing clock signal (F.sub.-- SYNC) indicative of the desired motor operating speed control loop generates two analog voltage signals, V.sub.-- TACH and V.sub.-- SYNC, from frequency signals F.sub.-- TACH and F.sub.-- SYNC, and generates an error voltage signal proportional to the difference between these two voltage signals. Each frequency signal is first converted into a binary number signal proportional to the associated motor period (inverse frequency). Each such binary number signal is then converted to an analog voltage signal having magnitude proportional to the motor frequency. Each analog voltage signal is thus produced by a two-step process employing the successive reciprocal (division) elements. The nonlinearities introduced by the successive reciprocal elements substantially cancel so that each analog voltage signal is linear with motor speed. The speed, accuracy, and linearity of this frequency-to-voltage conversion method allows continuously variable speed operation with constant loop parameters and wide loop bandwidth. The phase control loop of the invention includes a ramp generator, and a sample and hold unit. The ramp generator integrates the frequency derived voltage V.sub.-- SYNC. Thus, the ramp's amplitude is constant regardless of variations in the frequency of signal F.sub.-- SYNC, and the phase control loop is adapted for continuously variable speed operation. The ramp voltage is sampled by F.sub.-- TACH, the sampled voltage is amplified and employed as an error signal for controlling the motor phase.

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San Carlos, CA, United States of America

Michael B Shields