Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Michael B Raynham

Myron R Tuttle

Minh H Nguyen

Hans A Wiggers

James K Gendreau

Brian E Donne

Andy Kim Yu

A single-IC subsystem controller for controlling electronic devices and subsystems within computer systems and other large electronic systems. The single-IC subsystem controller includes a micro-controller, a complex programmable logic device, an EEPROM, an SRAM, and various electronic bus interfaces and additional signal long interfaces for interfacing the single-IC subsystem controller device to electronic devices and electrical components. The single-IC subsystem controller allows for flexible partitioning of control functionality between hardware circuits programmed into the CPLD and software routines executed by the micro-controller.

Integrated micro-controller and programmable device

A memory controller emulator for controlling memory devices in a memory system includes a counter for generating a plurality of address values. A plurality of storage devices for storing memory address information, memory data to be stored in the memory devices, and memory commands for controlling operation of the memory devices, are coupled to the counter. Each of the plurality of storage devices is configured to output data stored therein based upon address values received from the counter.

Memory controller emulator for controlling memory devices in a memory system

A wireless diagnostic system for diagnosing a problem with at least one server includes a portable diagnostic tool. The portable diagnostic tool includes a wireless transmitter and a wireless receiver. The portable diagnostic tool is configured to transmit requests with the tool's wireless transmitter. A wireless communication subsystem is coupled to a first server. The wireless communication subsystem includes a wireless transmitter and a wireless receiver. The wireless communication subsystem is configured to receive a transmitted request from the portable diagnostic tool with the subsystem's wireless receiver. The wireless communication subsystem is configured to transmit service information with the subsystem's wireless transmitter in response to a received request. The portable diagnostic tool is configured to receive the service information with the tool's wireless receiver.

Wireless server diagnostic system and method

A server system includes a cartridge cage including a power supply. The server system includes a plurality of server cartridges. Each server cartridge is configured to be inserted into the cartridge cage and be powered by the cartridge cage power supply. Each server cartridge includes a processor, memory, and a non-volatile storage device. Each server cartridge includes a case substantially surrounding the processor, the memory, and the non-volatile storage device. The server system includes a cooling subsystem positioned between the power supply and the plurality of server cartridges.

Server system with removable server cartridges

The present invention provides a memory configuration that is comprised of a memory controller, a single central switch, a data bus that is electrically coupled to the memory controller and the central switch, and a plurality of N memory modules, where each of the plurality of N memory modules is radially connected to the central switch by a corresponding memory module bus. The central switch is physically located on the motherboard and helps to provide in combination with the parallel connection of the memory modules, a point to point bus between the memory controller and the memory device on the memory module. The memory modules are field replaceable units and are electrically isolated from each other for use in high availability fault tolerant systems.

Radial arm memory bus for a high availability computer system

The present invention provides a process and memory configuration for providing chipkill error detection in a low end server without requiring non-standard components or additional memory devices. Typically, the number of error correction bits required for chipkill functionality is dependent on the width of the memory chip to be corrected and the CRC algorithm that is used. If the required number of error correction bits is not provided by the memory system, another option according to the present invention, is to perform doubleword operation for consecutive memory locations in a single DIMM module. Reading the memory module in double words basically provides the system with double its previous number of ECC bits per data transfer. Since these low end systems would typically not have the number of error correction bits necessary to do the chipkill operation, this double word technique allows chipkill for low end systems which would normally not be able to perform the chipkill operation.

Chipkill for a low end server or workstation

A memory device responsive to command signals includes multiple banks of memory arrays. Each bank includes a plurality of primary storage cells and a spare unit of spare storage cells. A detector detects an error in a first unit of the primary storage cells in a first one of the banks. A controller responsive to command signals automatically re-maps the first unit of the primary storage cells to the spare unit of storage cells, without interrupting access to memory data.

Self-healing memory

A memory module within a computing system includes a management memory. The management memory provides permanent storage for management information. For example, an error log is stored within the management memory. The error log indicates a time stamp for errors which occur in operation of the memory module. The error log consists of, for example, two lists. A first list indicates a time stamp for each (soft) correctable error which occurs in operation of the memory module. A second list indicates a time stamp for each (hard) non-correctable error which occurs in operation of the memory module.

Management of memory modules

The present invention provides a low cost, low complexity, redundant power supply for an electronic data system. The low complexity of the system minimizes system failure rate while the redundancy improves system availability. The redundant power supply interconnect system is comprised of: a first electronic device including a first power supply; a second electronic device including a control means, a second power supply and a third power supply, wherein the first power supply means of the first electronic device is electrically coupled to the control means of the second electronic device; a first dedicated bus electrically coupling the first electronic device to the second electronic device; and a first serial management bus, the first serial management bus electrically coupling the first electronic device to the control means of the second electronic device.

Redundant power supply and storage system

Within a power supply, the draw of power between redundant power sources are passively balanced. Within a power plane of the printed circuit board a first current distribution plane section is placed. First connector pins are used to electrically connect the first current distribution plane to the first power source. Second connector pins are used to electrically connect the first current distribution plane to the second power source. Moats are placed within the power plane of the printed circuit board so that within the first current distribution plane section a first current path from the first connector pins to a first central power distribution area is substantially symmetrical to a second current path from the second connector pins to the first central power distribution area. Output power current passes through the first central power distribution area.

Balancing power distribution in a power supply system with redundant

Error detection or correction is provided on the same chip as DRAM memory. Because data and error correction bits need not travel on an external bus, error detection/correction can be conducted on a larger number of bits than the width of the data bus. When using memories which provide for access to a row of memory, such as static-column or fast-page mode memories, error correction is conducted on an entire row of memory during one error correction cycle. Following operations of the correction cycle, the data within a row of memory can be accessed independently of the EC circuitry.

Dram on-chip error correction/detection

A decoder-encoder with a biphase or delta-distance to binary decoding circuit adapts the data sampling interval to compensate for a non-centered signal level transition in the preceding sample interval. The location of the signal level transition in the prior sampling interval modifies the location of the subsequent sampling interval. The adaptive sampling maintains relative frequency and phase synchronization between the biphase or delta-distance source and the decoding circuit.

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Los Gatos, CA, United States of America

Michael B Raynham