Silicon Graphics, Incorporated

Michael B Nagy

Marc R Hannah

Robert Allen Shaw

Peter R Birch

John C Lin

A method and apparatus for producing output values corresponding to pixels of an input image. A coordinate translation circuit for is provided for performing coordinate translation from input pixel color components to corresponding texture coordinates. The texture coordinates collectively determine a texture address. The coordinate translation circuit also generates a set of interpolation factors in one embodiment used to resample around the point in texture space defined by the texture address. An interpolation circuit is coupled to the coordinate translation circuit to receive the texture address and the set of interpolation factors. The interpolation circuit uses the texture address and the set of interpolation factors to produce an output value. Typically, the output value represents a multidimensional lookup of the color components interpolated into multidimensional space. An application of the method and device of the invention includes a color conversion method for converting input pixel color components from a source color space to a destination color space.

Texture mapping circuit for performing data interpolations

A method is used to access a sub-region of a two or more dimensional data region, in which said region is composed of a patchwork of individually addressable tiles. A hardware assisted mechanism is used to address, reformat, and composite data from each tile to produce a row-major subregion data stream to the consuming device. This method abstracts information about how the desired region is stored and addressed, so that further processing steps can process the data as a contiguous two or more dimensional space without regard to how the data is composited. This is particularly useful for doing image processing on graphics processing systems where source data is often stored in separately managed and addressed tiles.

Apparatus and method for accelerated tiled data retrieval

In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored in memory. The interpolated texel value is output by the semiconductor chip, thereby minimizing transmission bandwidth as well as redundant storage of texture maps in a multi-processor environment.

Apparatus and method for integrating texture memory and interpolation

A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative, time saving functionality during read and write operations. During a write operation, the latch can receive only those byte(s) or a row of bytes to be written. Corresponding mask bits are set to indicate those bytes to be written. Logic in the device transfers only those bytes in the row to be written to the sense amplifiers for writing to memory, leaving the data of remaining bytes in memory intact. Read operations are rendered more efficient by enabling logic, coupled to column select logic, to automatically transfer from the latch the byte selected by the column select logic and the adjacent byte. This time saving feature is particularly useful for computer graphics applications which utilize linear interpolation processes.

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San Ramon, CA, United States of America

Michael B Nagy