International Business Machines Corporation

Michael B Kugel

Juergen Pille

Alexander Fritsch

Tobias Werner

Wolfgang Penth

Dieter F Wendel

Rolf Sautter

Yuen H Chan

Harry S Barowski

Stefan Payer

Werner Juchmes

Otto Andreas Torreiter

Raphael C Polig

Martin Eckert

Silke Penth

Gerhard Hellner

William Vincent Huott

Tilman Gloekler

Thomas Gentner

Thuyen Le

Ulrich Krauch

Matthias Woehrle

Alejandro Alberto Cook Lobo

Shankar Kalyanasundaram

Amira Rozenfeld

A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.

True complement dynamic circuit and method for combining binary data

A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

Logic built-in self-test of an electronic circuit

Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scannable storage element has both a scannable storage element output and a set of flip-flops. A memory array is connected with the scannable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.

Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature

Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.

A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.

Current-mode sense amplifier

A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.

Automated stressing and testing of semiconductor memory cells

An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal. The amplifier is further configured to generate a second logical value at the first output terminal of the amplifier in response to the sense current being higher than the reference current.

Current-mode sense amplifier and reference current circuitry

A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.

A memory cell that is readable through a bit line and addressable through a word line can be stressed using a method that includes addressing the memory cell, through the word line, for an addressing time. The memory cell can be stressed by applying a stress voltage to the bit line for a stress voltage time that overlaps with the addressing time for a stress time &#x394;t. A method for testing a memory cell can include writing a data value into the memory cell, stressing the memory cell, reading a stored value from the memory cell and determining whether the stored value corresponds to the data value. A testable memory array can include at least one memory cell that is addressable through a word line and readable through a bit line and a stress circuit for applying a stress voltage to the bit line.

Stressing and testing semiconductor memory cells

Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

RAM at speed flexible timing and setup control

The invention relates to a current sense amplifier () comprising a reference current input terminal (), a sense control line input terminal (), a sense current input terminal (), a first output terminal (), and a second output terminal (). The amplifier further comprises a first NAND gate () comprising an output terminal being connected to the first output terminal (), a second NAND gate () comprising an output terminal being connected to the second output terminal (), a first (T, T) and a second (T, T) cross coupled inverters, the first inverter comprising a first n-FET (T) and the second inverter comprising a second n-FET (T), a transmission gate () comprising a first and a second transmission terminal and a transmission control terminal, the transmission control terminal being connected to the sense control line input terminal (), an AND gate () having a first input terminal connected to the first output terminal () and a second input terminal connected to the second output terminal (), a third n-FET (T) having a gate connected to an output terminal of the AND gate (), a drain connected to the sense current input terminal, a source connected to ground, wherein a source of the first n-FET is connected to the sense current input terminal and a source of the second n-FET is connected to the reference current input terminal, a first input terminal of the first NAND gate and a first input terminal of the second NAND gate are connected to the sense control line input terminal, the first transmission terminal and a second input terminal of the first NAND gate are connected to an output terminal of the second inverter and the second transmission terminal and a second input terminal of the second NAND gate are connected to an output terminal of the first inverter.

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Boeblingen, Germany

Michael B Kugel