Emc Corporation

Digital Equipment Corporation

Michael B Evans

Uday K Gupta

Charles H Hopkins

Michael A Gagliardo

Hansel A Collins

John J Lynch

James E Tessari

Kumar Chinnaswamy

Timothy P Fissette

Donald F Hooper

Tryggve Fossum

John T Cardente

R Stephen Polzin

John Forecast

Stephen A Fridella

Ricky C Hetherington

Ronald M Salett

John E Murray

William R Grundmann

William C Whitney

James Theodore Compton

Gerald Cotter

Rueysen Lin

Richard C Beaven

Brian F Rost

Dave M Tongel

Described are techniques for performing recovery processing in a data storage system. A providing a flash-based memory is provided with includes cached write data that has not been destaged to a data storage device. It is determined whether said flash-based memory has a threshold amount of storage available thereon. If the flash-based memory does not have the threshold amount of storage available thereon, portions of the cache write data are destaged until said flash-based memory has a threshold amount of storage available thereon. Received data requests are processed in accordance with a first policy different from a second policy used in connection with processing received data requests if said flash-based memory has a threshold amount of storage available thereon.

Techniques for caching data using a volatile memory cache and solid state drive

A device for providing a plurality of virtual machines utilizes a multi-core processor having a plurality of cores, each with a memory cache, and a shared memory resource in communication with the cores. The device utilizes a cooperative, multi-level scheduler. The multi-level scheduler includes a primary scheduler and a plurality of secondary schedulers, each supporting a subset of the physical cores. The primary scheduler assigns a group of threads to one of the processor cores. The secondary scheduler associated with the processor core to which the group of threads was assigned schedules execution of individual ones of the threads. The secondary scheduler also provides an indication of lock status to the primary scheduler. The lock status information can be used by the primary scheduler to avoid preempting a thread that holds a lock.

Cooperative multi-level scheduler for virtual engines

Methods, systems, and computer program products for managing quality of service for shared storage accessed by a plurality of nodes are disclosed. According to one method, at a node of a plurality of nodes sharing access to a first disk array, quality-of-service (QoS) metadata associated with a portion of the disk array are requested from a server, wherein the QoS metadata includes at least one performance criterion for the portion of the disk array. I/O performance is monitored for the portion of the disk array in response to receiving the QoS metadata. The monitored I/O performance is compared with the QoS metadata. Based upon the comparison of the monitored I/O performance with the QoS metadata, it is determined whether a QoS violation has occurred. In response to determining that a QoS violation has occurred, the server is requested to migrate data associated with the portion of the disk array.

Methods systems, and computer program products for managing quality-of-service associated with storage shared by computing grids and clusters with a plurality of nodes

A method is used in managing data on data storage systems. Rules are defined for candidate data unit selection. The rules are automatically executed on a primary data storage system to examine data units on the primary data storage system. The rules are applied to the data units. A data unit is identified that matches the rules and the identified data unit is migrated. The identified data unit is copied from the primary storage system to a secondary storage system. The identified data unit on the primary storage system is replaced with metadata. the data storage space in the primary storage system corresponding to the identified data unit is freed up.

Managing data on data storage systems

Techniques for using flash-based memory in recovery processing

Described are techniques for managing data in a data storage system. While the data storage system is operating in a first mode, portions of cached write data not yet destaged to a data storage device are copied from the volatile memory cache to a first area in a flash-based memory. In response to a vault operation event, the data storage system operates in a second mode in which all remaining portions of cached write data from the volatile memory cache not currently included in the first area are copied to a second area of the flash-based memory.

Techniques for using flash-based memory as a write cache and a vault

In a distributed interactive multimedia service system, a client application of a set-top box located at a customer premises generates an attach request. A session manager, in response to receiving the attach request via a network, generates an allocation request and a create request. A resource manager, in response to the allocation request, allocates resources of a plurality of multimedia servers. The resources can include processor, memory, disk, and network resources. A media stream manager, in response to the create request, creates a multimedia stream. The session manager, in response to the resources being allocated, and the multimedia stream being created, launches a selected one of a plurality of multimedia services in the plurality of multimedia servers. The selected service provides multimedia information to the set-top box via the multimedia stream. The system includes a memory storing the plurality of multimedia services in a hierarchical tree structure having nodes representing composite and elemental services.

Distributed interactive multimedia service system

Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.

Method and apparatus for performing diagnosis scanning of a memory unit

Mode switching for a memory system with diagnostic scan

A computer system includes a plurality of central processing units (CPUs), a main memory, a system control unit (SCU) for controlling the transfer of data between the CPUs and the main memory, and a service processing unit (SPU) to interface the computer system with the outside world, such as an operator console. The method used for interfacing the SPU and SCU includes delivering a BUFFER FULL handshaking signal from the SPU to the SCU in response to the SPU receive buffer having data contained therein and being unavailable to receive data. The SCU responds to the absence of the BUFFER FULL handshaking signal by delivering a TRANSMIT FRAME handshaking signal to the SCU. A preselected duration of time after delivering the transmit frame, the SCU delivers the actual data in a series of fourteen consecutive clock cycles. Further, the method for delivering data from the transmit buffer of the SPU to a receive buffer of the SCU includes delivering a BUFFER REQUEST handshaking signal from the SPU to the SCU in order to determine if a buffer is currently available in the SCU. When a receive buffer grant becomes available in the SCU, a buffer grant handshaking signal is delivered to the SPU. The SPU responds by delivering the actual data in fourteen consecutive clock cycles.

Interface between a system control unit and a service processing unit of

In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is indentified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

Method and apparatus for detecting and correcting errors in a pipelined

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Upton, MA, United States of America

Michael B Evans